summaryrefslogtreecommitdiff
path: root/configs/tested-cfgs/SM7_QV100/gpgpusim.config
diff options
context:
space:
mode:
authorMahmoud Khairy A. Abdallah <[email protected]>2021-05-19 22:20:56 -0400
committerMahmoud Khairy A. Abdallah <[email protected]>2021-05-19 22:20:56 -0400
commit7fac247e3e1c4326081c3ea4d46da6c5dc83ccb9 (patch)
tree6f45c4e4450fb53e55834a37fcc8ad7c3ca4210b /configs/tested-cfgs/SM7_QV100/gpgpusim.config
parentb466afea67e6d6faf49f01ecfe378257fbdb93af (diff)
change L1 cache config in Volta+ to be write-through and write-allocate based on recent ubench
Diffstat (limited to 'configs/tested-cfgs/SM7_QV100/gpgpusim.config')
-rw-r--r--configs/tested-cfgs/SM7_QV100/gpgpusim.config2
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 47bf1c8..5f22a42 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -117,7 +117,7 @@
-gpgpu_unified_l1d_size 128
# L1 cache configuration
-gpgpu_l1_banks 4
--gpgpu_cache:dl1 S:4:128:64,L:L:m:N:L,A:512:8,16:0,32
+-gpgpu_cache:dl1 S:4:128:64,L:T:m:L:L,A:512:8,16:0,32
-gpgpu_l1_cache_write_ratio 25
-gpgpu_l1_latency 20
-gpgpu_gmem_skip_L1D 0