diff options
| author | Mahmoud <[email protected]> | 2019-08-26 12:17:52 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-08-26 12:17:52 -0400 |
| commit | c2a1e3a668f9a88239184e13460f7e1725b15c90 (patch) | |
| tree | 0546cc50d6e222072add55e36999a338b925d807 /configs/tested-cfgs/SM7_QV100 | |
| parent | 56c52cf6c4b369e9fd05759e9b16ea37ff6e332c (diff) | |
Banked L1, adding iSLIP and RR arbiteratio and adding some comments
Diffstat (limited to 'configs/tested-cfgs/SM7_QV100')
| -rw-r--r-- | configs/tested-cfgs/SM7_QV100/gpgpusim.config | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index f70ad55..f807e11 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -87,9 +87,10 @@ # if the assigned shd mem = 0, then L1 cache = 128KB # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution --adaptive_volta_cache_config 1 -# Volta unified cache has four ports --mem_unit_ports 4 +-adaptive_cache_config 1 +# Volta unified cache has four banks +-l1_banks 4 +#-mem_unit_ports 4 -gpgpu_cache:dl1 S:4:128:64,L:L:s:N:L,A:256:8,16:0,32 -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 @@ -97,8 +98,8 @@ -gmem_skip_L1D 0 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 --l1_latency 80 --smem_latency 19 +-l1_latency 20 +-smem_latency 20 -gpgpu_flush_l1_cache 1 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache |