diff options
| author | Fangjia Shen <[email protected]> | 2023-06-17 19:03:31 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-06-17 19:03:31 -0400 |
| commit | 301be9e59c6c934f4e194cf6c95dd0c60b3894cc (patch) | |
| tree | f1c25eaf864c908b5e79694d0fa9e4a62ffe3481 /configs/tested-cfgs/SM7_TITANV/gpgpusim.config | |
| parent | 66ae8815dd1a9cd5fcc0e08332ebca323c356863 (diff) | |
137 drop sector cache flexibility (#57)
Addresses accel-sim issue 137. For sector cache, the sector size must be 32B (hard-coded and not configurable) and cache line size must be set to 128B; a runtime parameter check will terminate simulation if the cache line size is not 128B.
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index af561de..c37aaf0 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -107,7 +107,7 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory # In Volta, we assign the remaining shared memory to L1 cache |