diff options
| author | Mahmoud <[email protected]> | 2019-04-25 15:39:13 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-04-25 15:39:13 -0400 |
| commit | 7764a7f373a0f99d714d42fcb380fb48e00b9c54 (patch) | |
| tree | 6cdc89f7c0211fb96ff387f745df1a279b4e7c30 /configs/tested-cfgs/SM7_TITANV/gpgpusim.config | |
| parent | ec2ada3b5f2ef91341d30e8f56f3c4d9ecafb2a4 (diff) | |
updating titanv config file
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV/gpgpusim.config')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 8ed4cd0..f48e897 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -1,4 +1,4 @@ -# This config models the Volta Titan X +# This config models the Volta Titan V # For more info about volta architecture: # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# @@ -25,7 +25,7 @@ # volta clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> -# Volta NVIDIA V100 clock domains are adopted from +# Volta NVIDIA TITANV clock domains are adopted from # https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 # boost mode @@ -42,7 +42,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core +## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 @@ -104,7 +104,7 @@ # Volta has sub core model, in which each scheduler has its own reisiter file and EUs # i.e. schedulers are isolated --sub_core_model 0 +-sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 @@ -125,7 +125,7 @@ # interconnection -network_mode 1 --inter_config_file config_fermi_islip.icnt +-inter_config_file config_volta_islip.icnt # memory partition latency config -rop_latency 120 @@ -150,7 +150,7 @@ #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47: # CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4" -# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ +# Timing for 850 MHZ, Tesla TITANV HBM runs at 850 MHZ -gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40: CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3" @@ -163,7 +163,7 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Pascal has two schedulers per core +# Volta has four schedulers per core -gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 @@ -178,7 +178,7 @@ -enable_ptx_file_line_stats 1 -visualizer_enabled 0 -# power model configs, disable it untill we create a real energy model for Pascal 100 +# power model configs, disable it untill we create a real energy model for Volta -power_simulation_enabled 0 # tracing functionality |