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| author | Ahmad Alawneh <[email protected]> | 2023-07-05 17:52:15 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2023-07-05 17:52:15 -0400 |
| commit | 1ce9febc61ab0e50c01ceea424cbf3e12a149366 (patch) | |
| tree | 61bba4462fde2ba21e00a166a952edd1087b9ca9 /configs/tested-cfgs/SM7_TITANV | |
| parent | 5831da33a0421de19a34b628813be86bc73b9f91 (diff) | |
| parent | 58beccb510bb892de56b466ac764f24297affebd (diff) | |
Merge branch 'dev' into all_warn
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index af561de..c37aaf0 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -107,7 +107,7 @@ -gpgpu_dual_issue_diff_exec_units 1 ## L1/shared memory configuration -# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> +# <sector?>:<nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo # Defualt config is 32KB DL1 and 96KB shared memory # In Volta, we assign the remaining shared memory to L1 cache |