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| author | mkhairy <[email protected]> | 2021-05-19 17:51:00 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2021-05-19 17:51:00 -0400 |
| commit | 2b2b6a2916e4ed833c707be887bf927167a71fa6 (patch) | |
| tree | 526646c9ac3f182e9fd7103255e3680f2fcc7adc /configs/tested-cfgs/SM7_TITANV | |
| parent | 0e4f12ae3fefd6bad6175014411a6587a3898ac8 (diff) | |
| parent | 1875132a20422404ea75d04fc7be58a1bbca48f3 (diff) | |
Merge pull request #15 from JRPan/adaptive-cache
Adaptive cache
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3fa51ee..3e080bc 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -125,6 +125,9 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_l1_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 |