diff options
| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2021-05-19 19:39:48 -0400 |
|---|---|---|
| committer | Mahmoud Khairy A. Abdallah <[email protected]> | 2021-05-19 19:39:48 -0400 |
| commit | a2ba2f57e8a24b9dd6ec6f2568accbbf439a9dca (patch) | |
| tree | 6fd4831d23585ac882bd39d6314bc6dee605c058 /configs/tested-cfgs/SM7_TITANV | |
| parent | 604baaf59255776b4714c0270ce36ad823d34df4 (diff) | |
updating config files with right adaptive cache parameters
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 32245d7..e7f7305 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -114,20 +114,21 @@ # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x # disable this mode in case of multi kernels/apps execution -gpgpu_adaptive_cache_config 1 -# Volta unified cache has four banks +-gpgpu_shmem_option 0,8,16,32,64,96 +-gpgpu_unified_l1d_size 128 +# L1 cache configuration -gpgpu_l1_banks 4 -gpgpu_cache:dl1 S:1:128:256,L:L:m:N:L,A:512:8,16:0,32 +-gpgpu_l1_cache_write_ratio 25 +-gpgpu_gmem_skip_L1D 0 +-gpgpu_l1_latency 20 +-gpgpu_flush_l1_cache 1 +-gpgpu_n_cluster_ejection_buffer_size 32 +# shared memory configuration -gpgpu_shmem_size 98304 -gpgpu_shmem_sizeDefault 98304 -gpgpu_shmem_per_block 65536 --gpgpu_gmem_skip_L1D 0 --gpgpu_n_cluster_ejection_buffer_size 32 --gpgpu_l1_latency 20 -gpgpu_smem_latency 20 --gpgpu_flush_l1_cache 1 --gpgpu_l1_cache_write_ratio 25 --gpgpu_shmem_option 0,12,24,48,96 --gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 |