diff options
| author | Mahmoud <[email protected]> | 2019-04-25 15:39:13 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-04-25 15:39:13 -0400 |
| commit | 7764a7f373a0f99d714d42fcb380fb48e00b9c54 (patch) | |
| tree | 6cdc89f7c0211fb96ff387f745df1a279b4e7c30 /configs/tested-cfgs/SM7_TITANV_fastlocalxbar | |
| parent | ec2ada3b5f2ef91341d30e8f56f3c4d9ecafb2a4 (diff) | |
updating titanv config file
Diffstat (limited to 'configs/tested-cfgs/SM7_TITANV_fastlocalxbar')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config index 73516e1..3e4a8fa 100644 --- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config @@ -1,4 +1,4 @@ -# This config models the Volta Titan X +# This config models the Volta Titan V # For more info about volta architecture: # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# @@ -25,7 +25,7 @@ # volta clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> -# Volta NVIDIA V100 clock domains are adopted from +# Volta NVIDIA TITANV clock domains are adopted from # https://en.wikipedia.org/wiki/Volta_(microarchitecture) -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0 # boost mode @@ -42,7 +42,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core +## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 @@ -123,9 +123,8 @@ -gpgpu_max_insn_issue_per_warp 1 -gpgpu_dual_issue_diff_exec_units 1 -# interconnection +# use local xbar interconnection -network_mode 2 --inter_config_file config_fermi_islip.icnt -inct_in_buffer_limit 512 -inct_out_buffer_limit 512 -inct_subnets 2 @@ -167,7 +166,7 @@ #-Seperate_Write_Queue_Enable 1 #-Write_Queue_Size 64:56:32 -# Pascal has two schedulers per core +# Volta has four schedulers per core -gpgpu_num_sched_per_core 4 # Two Level Scheduler with active and pending pools #-gpgpu_scheduler two_level_active:6:0:1 @@ -182,7 +181,7 @@ -enable_ptx_file_line_stats 1 -visualizer_enabled 0 -# power model configs, disable it untill we create a real energy model for Pascal 100 +# power model configs, disable it untill we create a real energy model for Volta -power_simulation_enabled 0 # tracing functionality |