diff options
| author | Mahmoud Khairy A. Abdallah <[email protected]> | 2020-04-02 21:41:01 -0400 |
|---|---|---|
| committer | Mahmoud Khairy A. Abdallah <[email protected]> | 2020-04-02 21:41:01 -0400 |
| commit | fe8dd7eadbb67b9e917c92c9c540812db35fce37 (patch) | |
| tree | e63ed5b5ce5e0ebd424492cf6b28e58f0f9f5630 /configs/tested-cfgs | |
| parent | f9e65c53a29b89c167e713afa6d5eb92709047af (diff) | |
updating the turing config
Diffstat (limited to 'configs/tested-cfgs')
| -rw-r--r-- | configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config | 2 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 18 |
2 files changed, 10 insertions, 10 deletions
diff --git a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config index 1951a3f..77617d6 100644 --- a/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config +++ b/configs/tested-cfgs/SM3_KEPLER_TITAN/gpgpusim.config @@ -40,7 +40,7 @@ -gpgpu_shader_registers 65536 -gpgpu_occupancy_sm_number 62 -# This implies a maximum of 32 warps/SM +# This implies a maximum of 64 warps/SM -gpgpu_shader_core_pipeline 2048:32 -gpgpu_shader_cta 16 -gpgpu_simd_model 1 diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 9d3992a..e8329dd 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -1,12 +1,12 @@ # This config models the Turing RTX 2060 # For more info about turing architecture: -# https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf -# "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 +# 1- https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf +# 2- "RTX on—The NVIDIA Turing GPU", IEEE MICRO 2020 # functional simulator specification -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 --gpgpu_ptx_force_max_capability 70 +-gpgpu_ptx_force_max_capability 75 # Device Limits -gpgpu_stack_size_limit 1024 @@ -33,17 +33,17 @@ # volta clock domains #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock> --gpgpu_clock_domains 1365.0:1365.0:1365.0:3500.0 +-gpgpu_clock_domains 1365.0:1365.0:1365.0:7000.0 # boost mode -# -gpgpu_clock_domains 1680.0:1680.0:1680.0:3500.0 +# -gpgpu_clock_domains 1680.0:1680.0:1680.0:7000.0 # shader core pipeline config -gpgpu_shader_registers 65536 -gpgpu_registers_per_block 65536 -gpgpu_occupancy_sm_number 75 -# This implies a maximum of 64 warps/SM --gpgpu_shader_core_pipeline 2048:32 +# This implies a maximum of 32 warps/SM +-gpgpu_shader_core_pipeline 1024:32 -gpgpu_shader_cta 32 -gpgpu_simd_model 1 @@ -89,7 +89,7 @@ -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 --gpgpu_coalesce_arch 60 +-gpgpu_coalesce_arch 75 ## In Turing, a warp scheduler can issue 1 inst per cycle -gpgpu_max_insn_issue_per_warp 1 @@ -156,7 +156,7 @@ -gpgpu_n_mem_per_ctrlr 1 -gpgpu_dram_buswidth 2 -gpgpu_dram_burst_length 16 --dram_data_command_freq_ratio 4 # GDDR6 is QDR +-dram_data_command_freq_ratio 2 # GDDR6 is configured as DDR in Turing -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS |