diff options
| author | Tim Rogers <[email protected]> | 2018-11-05 21:50:40 -0500 |
|---|---|---|
| committer | GitHub <[email protected]> | 2018-11-05 21:50:40 -0500 |
| commit | 0265d747b06c18d0a1ee00fb1641032201425c97 (patch) | |
| tree | 9547bddfcc1c124deac5334dfae85a4a051002c4 /configs | |
| parent | 42d8d8c9b5b0eb93ff228a877fd6a5bed5cf956d (diff) | |
| parent | b150969498792d50583674947d7c240cd6a11a68 (diff) | |
Merge pull request #80 from AamirRaihan/dev
Merging Tensor Cores code
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index c8351da..7532c01 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -12,6 +12,7 @@ -gpgpu_ptx_instruction_classification 0 -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 70 +-gpgpu_tensor_core_avail 1 # SASS execution (only supported with CUDA >= 4.0) -gpgpu_ptx_convert_to_ptxplus 0 @@ -41,14 +42,13 @@ -gpgpu_simd_model 1 # Pipeline widths and number of FUs -# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB +# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE ## Volta GV100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12,1,1 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 -gpgpu_num_dp_units 4 - # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" # All Div operations are executed on SFU unit |