GeForceGTX750Ti correlation setup. Modified config file to reflect GTX750Ti architecture. Modified shader.h to allow for larger CTA per warp, to accomodate Maxwell specs.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21798]

2 files changed, 88 insertions, 17 deletions

diff --git a/configs/GeForceGTX750Ti/config_fermi_islip.icnt b/configs/GeForceGTX750Ti/config_fermi_islip.icnt
new file mode 100644
index 0000000..7820e4e
--- /dev/null
+++ b/configs/GeForceGTX750Ti/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 27;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config
index 436cb41..5b5ee90 100644
--- a/configs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/GeForceGTX750Ti/gpgpusim.config
@@ -9,22 +9,22 @@
 -gpgpu_ptx_save_converted_ptxplus 0
 
 # high level architecture configuration
--gpgpu_n_clusters 15
+-gpgpu_n_clusters 5
 -gpgpu_n_cores_per_cluster 1
--gpgpu_n_mem 6
--gpgpu_n_sub_partition_per_mchannel 2 
+-gpgpu_n_mem 2
+-gpgpu_n_sub_partition_per_mchannel 1 
 
 # Fermi clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
 # by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
--gpgpu_clock_domains 700.0:700.0:700.0:924.0
+-gpgpu_clock_domains 1080.0:1080.0:1080.0:1335.0
 
 # shader core pipeline config
--gpgpu_shader_registers 32768
+-gpgpu_shader_registers 65536
 
 # This implies a maximum of 48 warps/SM
--gpgpu_shader_core_pipeline 1536:32 
+-gpgpu_shader_core_pipeline 2048:32 
 -gpgpu_shader_cta 8
 -gpgpu_simd_model 1 
 
@@ -32,13 +32,13 @@
 # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
 -gpgpu_pipeline_widths 2,1,1,2,1,1,2
 -gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 1
+-gpgpu_num_sfu_units 8
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_latency_int 6,12,13,13,210
 -ptx_opcode_initiation_int 1,2,2,1,8
--ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_latency_fp 6,12,6,6,374
 -ptx_opcode_initiation_fp 1,2,1,1,4
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,16,8,8,130
@@ -49,14 +49,15 @@
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 -gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
--gpgpu_shmem_size 49152
+-gpgpu_shmem_size 65536
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
 #-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:32:8,8
 #-gpgpu_shmem_size 16384
 
 # 64 sets, each 128 bytes 8-way for each memory sub partition. This gives 786KB L2 cache
--gpgpu_cache:dl2 64:128:8,L:B:m:W:L,A:32:4,4:0,32
+# Ignore above. Maxwell has 2MB of L2 cache. Configuration is unknown, so making a guess.
+-gpgpu_cache:dl2 256:128:16,L:B:m:W:L,A:32:4,4:0,32
 -gpgpu_cache:dl2_texture_only 0 
 
 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
@@ -82,8 +83,8 @@
 -inter_config_file config_fermi_islip.icnt
 
 # memory partition latency config 
--rop_latency 120
--dram_latency 100
+-rop_latency 80
+-dram_latency 60
 
 # dram model config
 -gpgpu_dram_scheduler 1
@@ -96,7 +97,7 @@
 -gpgpu_dram_return_queue_size 116
 
 # for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
--gpgpu_n_mem_per_ctrlr 2
+-gpgpu_n_mem_per_ctrlr 4
 -gpgpu_dram_buswidth 4
 -gpgpu_dram_burst_length 8
 -dram_data_command_freq_ratio 4  # GDDR5 is QDR
@@ -108,8 +109,8 @@
 -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
                         CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
 
-# Fermi has two schedulers per core
--gpgpu_num_sched_per_core 2
+# Maxwell has four schedulers per core
+-gpgpu_num_sched_per_core 4
 # Two Level Scheduler with active and pending pools
 #-gpgpu_scheduler two_level_active:6:0:1
 # Loose round robbin scheduler
@@ -124,7 +125,7 @@
 -visualizer_enabled 0
 
 # power model configs
--power_simulation_enabled 1
+-power_simulation_enabled 0
 -gpuwattch_xml_file gpuwattch_gtx480.xml
 
 # tracing functionality