Changing the Titan X config file to use the last modifications

2 files changed, 29 insertions, 21 deletions

diff --git a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
index 602daee..58e596d 100644
--- a/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
+++ b/configs/Pascal-P102-GDDR5X/config_fermi_islip.icnt
@@ -1,6 +1,6 @@
 //21*1 fly with 32 flits per packet under gpgpusim injection mode
 use_map = 0;
-flit_size = 32; 
+flit_size = 40; 
 
 // currently we do not use this, see subnets below
 network_count = 2;
@@ -17,7 +17,7 @@ routing_function = dest_tag;
 // Flow control
 
 num_vcs     = 1;
-vc_buf_size = 8;
+vc_buf_size = 32;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config
index 8b02680..36d13af 100644
--- a/configs/Pascal-P102-GDDR5X/gpgpusim.config
+++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config
@@ -12,8 +12,9 @@
 -gpgpu_ptx_save_converted_ptxplus 0
 
 # high level architecture configuration
+# P102 has two semi-indp scheds per core, and two cores per cluster 
 -gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 1
+-gpgpu_n_cores_per_cluster 2
 -gpgpu_n_mem 12
 -gpgpu_n_sub_partition_per_mchannel 2 
 
@@ -24,20 +25,20 @@
 -gpgpu_clock_domains 1417.0:2834.0:1417.0:2500.0
 
 # shader core pipeline config
--gpgpu_shader_registers 65536
+-gpgpu_shader_registers 32768
 
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
+# This implies a maximum of 32 warps/SM
+-gpgpu_shader_core_pipeline 1024:32 
+-gpgpu_shader_cta 16
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
 ## Pascal GP102 has 4 SP SIMD units and 4 SFU units
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,4,1,4,1,4,1,9
--gpgpu_num_sp_units 4
--gpgpu_num_sfu_units 4
+-gpgpu_pipeline_widths 2,1,2,1,2,1,2,1,5
+-gpgpu_num_sp_units 2
+-gpgpu_num_sfu_units 2
 -gpgpu_num_dp_units 1
 
 
@@ -51,7 +52,6 @@
 -ptx_opcode_initiation_fp 1,2,1,1,4
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,8,8,8,130
--ptx_opcode_latency_sfu 8
 -ptx_opcode_initiation_sfu 4
 
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
@@ -60,13 +60,16 @@
 # Pascal GP102 has 96KB Shared memory
 # Pascal GP102 has 64KB L1 cache
 # The defulat is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,S:128:8,8
--gpgpu_shmem_size 98304
+-gpgpu_cache:dl1  S:64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_shmem_size 49152
 -gmem_skip_L1D 1
+-icnt_flit_size 40
+-gpgpu_n_cluster_ejection_buffer_size 32
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:4,4:0,32
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:256:4,4:0,32
 -gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -76,15 +79,14 @@
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
 
 # enable operand collector 
-## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
 -gpgpu_operand_collector_num_units_sp 12
 -gpgpu_operand_collector_num_units_sfu 6
 -gpgpu_operand_collector_num_units_mem 8
 -gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 4
--gpgpu_operand_collector_num_out_ports_sfu 4
+-gpgpu_operand_collector_num_in_ports_sp 2
+-gpgpu_operand_collector_num_out_ports_sp 2
+-gpgpu_operand_collector_num_in_ports_sfu 2
+-gpgpu_operand_collector_num_out_ports_sfu 2
 -gpgpu_operand_collector_num_in_ports_mem 1
 -gpgpu_operand_collector_num_out_ports_mem 1
 -gpgpu_operand_collector_num_in_ports_dp 1
@@ -119,7 +121,7 @@
 # the minimum DRAM latency (100 core cycles).  I.e. 
 #   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
+-gpgpu_dram_return_queue_size 192
 
 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
 # 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
@@ -136,8 +138,14 @@
 -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
                         CL=12:WL=4:CDLR=5:WR=12:nbkgrp=4:CCDL=3:RTPL=2"
 
+-dram_bnk_indexing_policy 0
+-dram_bnkgrp_indexing_policy 1
+
+#-Seperate_Write_Queue_Enable 1
+#-Write_Queue_Size 32:28:16
+
 # Pascal 102 has four schedulers per core
--gpgpu_num_sched_per_core 4
+-gpgpu_num_sched_per_core 2
 # Two Level Scheduler with active and pending pools
 #-gpgpu_scheduler two_level_active:6:0:1
 # Loose round robbin scheduler