Merge branch 'dev' into AerialVision_cache_support

6 files changed, 48 insertions, 18 deletions

diff --git a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
index fb044c6..3261d5a 100644
--- a/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
+++ b/configs/deprecated-cfgs/SM6_GTX1080/gpgpusim.config
@@ -31,12 +31,14 @@
 -gpgpu_simd_model 1 
 
 # Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
+# ID_OC_SP, ID_OC_DP, ID_OC_INT, ID_OC_SFU, ID_OC_MEM, OC_EX_SP, OC_EX_DP, OC_EX_INT, OC_EX_SFU, OC_EX_MEM, EX_WB
 ## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_pipeline_widths 4,0,0,1,1,4,0,0,1,1,6
 -gpgpu_num_sp_units 4
 -gpgpu_num_sfu_units 1
+-gpgpu_tensor_core_avail 0
+-gpgpu_num_tensor_core_units 0
 
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
@@ -54,20 +56,20 @@
 # Pascal GP102 has 96KB Shared memory
 # Pascal GP102 has 64KB L1 cache
 # The default is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,8
+-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,A:128:8,8
 -gpgpu_shmem_size 98304
 -gmem_skip_L1D 1
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
+-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:1024:1024,4:0,32 # used to be 128:4
 -gpgpu_cache:dl2_texture_only 0 
 
 # 4 KB Inst.
--gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4
 # 48 KB Tex 
--gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
 # 12 KB Const
--gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4
 
 # enable operand collector 
 ## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index d71b2fd..cf3627b 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -3,6 +3,13 @@
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 20 
 
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+
+# Compute Capability
+-gpgpu_compute_capability_major 2
+-gpgpu_compute_capability_minor 0
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
diff --git a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
index dec4789..dec4789 100644
--- a/configs/tested-cfgs/SM6_TITANX/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM6_TITANX/config_pascal_islip.icnt
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index cb23ab3..2fe898a 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -8,6 +8,16 @@
 -gpgpu_ptx_force_max_capability 61 
 -gpgpu_ignore_resources_limitation 1
 
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
+# Compute Capability
+-gpgpu_compute_capability_major 6
+-gpgpu_compute_capability_minor 1
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
@@ -92,7 +102,7 @@
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
 # 48 KB Tex 
-# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
+# Note, TEX is deprected in Pascal, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
diff --git a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt
index 615d0a9..615d0a9 100644
--- a/configs/tested-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/tested-cfgs/SM7_TITANV/config_volta_islip.icnt
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 8ed4cd0..ebd442f 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -1,4 +1,4 @@
-# This config models the Volta Titan X
+# This config models the Volta Titan V
 # For more info about volta architecture:
 # http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
 # https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
@@ -13,6 +13,17 @@
 -gpgpu_ptx_sim_mode 0
 -gpgpu_ptx_force_max_capability 70 
 
+
+# Device Limits
+-gpgpu_stack_size_limit 1024
+-gpgpu_heap_size_limit 8388608
+-gpgpu_runtime_sync_depth_limit 2
+-gpgpu_runtime_pending_launch_count_limit 2048
+
+# Compute Capability
+-gpgpu_compute_capability_major 7
+-gpgpu_compute_capability_minor 0
+
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
 -gpgpu_ptx_save_converted_ptxplus 0
@@ -25,7 +36,7 @@
 
 # volta clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Volta NVIDIA V100  clock domains are adopted from 
+# Volta NVIDIA TITANV  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
 -gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
 # boost mode
@@ -42,7 +53,7 @@
 
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE
-## Volta GV100 has 4 SP SIMD units, 4 SFU units, 4 DP units per core
+## Volta TITANV has 4 SP SIMD units, 4 INT units, 4 SFU units, 4 DP units per core, 4 Tensor core units
 ## we need to scale the number of pipeline registers to be equal to the number of SP units
 -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4
 -gpgpu_num_sp_units 4
@@ -75,7 +86,7 @@
 # if the assigned shd mem = 0, then L1 cache = 128KB
 # For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
 # disable this mode in case of multi kernels/apps execution
--adpative_volta_cache_config 1
+-adaptive_volta_cache_config 1
 # Volta unified cache has four ports
 -mem_unit_ports 4
 -gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
@@ -102,9 +113,9 @@
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4
 
-# Volta has sub core model, in which each scheduler has its own reisiter file and EUs
+# Volta has sub core model, in which each scheduler has its own register file and EUs
 # i.e. schedulers are isolated
--sub_core_model 0
+-sub_core_model 1
 # disable specialized operand collectors and use generic operand collectors instead
 -enable_specialized_operand_collector 0
 -gpgpu_operand_collector_num_units_gen 8
@@ -125,7 +136,7 @@
 
 # interconnection
 -network_mode 1 
--inter_config_file config_fermi_islip.icnt
+-inter_config_file config_volta_islip.icnt
 
 # memory partition latency config 
 -rop_latency 120
@@ -150,7 +161,7 @@
 #-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
 #                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
 
-# Timing for 850 MHZ, Tesla TITANV V100 HBM runs at 850 MHZ
+# Timing for 850 MHZ, Tesla TITANV HBM runs at 850 MHZ
 -gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=12:RAS=28:RP=12:RC=40:
                         CL=12:WL=2:CDLR=3:WR=10:nbkgrp=4:CCDL=2:RTPL=3"
 
@@ -163,7 +174,7 @@
 #-Seperate_Write_Queue_Enable 1
 #-Write_Queue_Size 64:56:32
 
-# Pascal has two schedulers per core
+# Volta has four schedulers per core
 -gpgpu_num_sched_per_core 4
 # Two Level Scheduler with active and pending pools
 #-gpgpu_scheduler two_level_active:6:0:1
@@ -178,7 +189,7 @@
 -enable_ptx_file_line_stats 1
 -visualizer_enabled 0
 
-# power model configs, disable it untill we create a real energy model for Pascal 100
+# power model configs, disable it untill we create a real energy model for Volta
 -power_simulation_enabled 0
 
 # tracing functionality