diff options
| author | Andrew M. B. Boktor <[email protected]> | 2012-05-05 10:50:00 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:19:37 -0700 |
| commit | 4505c33872fc5c665bee0060be1fdbfa8c77fdb6 (patch) | |
| tree | 43aebc65a027fbd58d76465514372f346e695411 /configs | |
| parent | 08f50cd087577727ff4f14049bb92514c763a14a (diff) | |
Configuring the opcode latencies and the number of function units
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12323]
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/Fermi/gpgpusim.config | 14 | ||||
| -rw-r--r-- | configs/QuadroFX5800/gpgpusim.config | 17 |
2 files changed, 30 insertions, 1 deletions
diff --git a/configs/Fermi/gpgpusim.config b/configs/Fermi/gpgpusim.config index d658c7f..afe86e7 100644 --- a/configs/Fermi/gpgpusim.config +++ b/configs/Fermi/gpgpusim.config @@ -22,6 +22,20 @@ -gpgpu_shader_cta 8 -gpgpu_simd_model 1 +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,1,1,1,1,1,1 +-gpgpu_num_sp_units 2 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 4,13,4,5,145 +-ptx_opcode_initiation_int 1,2,2,1,8 +-ptx_opcode_latency_fp 4,13,4,5,39 +-ptx_opcode_initiation_fp 1,2,1,1,4 +-ptx_opcode_latency_dp 8,19,8,8,330 +-ptx_opcode_initiation_dp 8,16,8,8,130 # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # <nsets>:<bsize>:<assoc>:<rep>:<wr>:<alloc>,<mshr>:<N>:<merge>,<mq> diff --git a/configs/QuadroFX5800/gpgpusim.config b/configs/QuadroFX5800/gpgpusim.config index e14d2f1..1dc09eb 100644 --- a/configs/QuadroFX5800/gpgpusim.config +++ b/configs/QuadroFX5800/gpgpusim.config @@ -13,7 +13,22 @@ -gpgpu_shader_registers 16384 -gpgpu_shader_core_pipeline 1024:32 -gpgpu_shader_cta 8 --gpgpu_simd_model 1 +-gpgpu_simd_model 1 + +# Pipeline widths and number of FUs +# ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB +-gpgpu_pipeline_widths 1,1,1,1,1,1,1 +-gpgpu_num_sp_units 1 +-gpgpu_num_sfu_units 1 + +# Instruction latencies and initiation intervals +# "ADD,MAX,MUL,MAD,DIV" +-ptx_opcode_latency_int 1,1,19,25,145 +-ptx_opcode_initiation_int 1,1,4,4,32 +-ptx_opcode_latency_fp 1,1,1,1,30 +-ptx_opcode_initiation_fp 1,1,1,1,5 +-ptx_opcode_latency_dp 8,8,8,8,335 +-ptx_opcode_initiation_dp 8,8,8,8,130 # memory stage behaviour -gpgpu_cache:il1 4:256:4:L:R:f,A:2:32,4 |