Made additional improvements to Maxwell correlation in config file such as merger of L1/Texture cache.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 21837]

1 files changed, 11 insertions, 15 deletions

diff --git a/configs/GeForceGTX750Ti/gpgpusim.config b/configs/GeForceGTX750Ti/gpgpusim.config
index 9a3d73b..afd3825 100644
--- a/configs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/GeForceGTX750Ti/gpgpusim.config
@@ -14,10 +14,9 @@
 -gpgpu_n_mem 2
 -gpgpu_n_sub_partition_per_mchannel 1
 
-# Fermi clock domains
+# Maxwell clock domains
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# In Fermi, each pipeline has 16 execution units, so the Core clock needs to be divided
-# by 2. (GPGPU-Sim simulates a warp (32 threads) in a single cycle). 1400/2 = 700
+# In Maxwell, each pipeline has 32 execution units, so the Core clock is just the reported number.
 -gpgpu_clock_domains 1137.0:1137.0:1137.0:2700.0
 
 # shader core pipeline config
@@ -31,7 +30,7 @@
 # Pipeline widths and number of FUs
 # ID_OC_SP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_SFU,OC_EX_MEM,EX_WB
 -gpgpu_pipeline_widths 2,1,1,2,1,1,2
--gpgpu_num_sp_units 2
+-gpgpu_num_sp_units 8
 -gpgpu_num_sfu_units 32
 
 # Instruction latencies and initiation intervals
@@ -43,11 +42,8 @@
 -ptx_opcode_latency_dp 8,19,8,8,330
 -ptx_opcode_initiation_dp 8,16,8,8,130
 
-# In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
--gpgpu_cache:dl1  32:128:4,L:L:m:N:H,A:32:8,8
+-gpgpu_cache:dl1 none
+# 32:128:4,L:L:m:N:H,A:32:8,8
 -gpgpu_shmem_size 65536
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
@@ -59,7 +55,7 @@
 -gpgpu_cache:dl2_texture_only 0 
 
 -gpgpu_cache:il1 4:128:4,L:R:f:N:L,A:2:32,4
--gpgpu_tex_cache:l1 4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 16:128:32,L:R:m:N:L,F:128:4,128:2
 -gpgpu_const_cache:l1 64:64:2,L:R:f:N:L,A:2:32,4
 
 # enable operand collector 
@@ -74,15 +70,15 @@
 -gpgpu_shmem_limited_broadcast 0
 -gpgpu_shmem_warp_parts 1
 
--gpgpu_max_insn_issue_per_warp 1
+-gpgpu_max_insn_issue_per_warp 2
 
 # interconnection
 -network_mode 1 
 -inter_config_file config_fermi_islip.icnt
 
 # memory partition latency config 
--rop_latency 120
--dram_latency 100
+-rop_latency 150
+-dram_latency 130
 
 # dram model config
 -gpgpu_dram_scheduler 1
@@ -92,9 +88,9 @@
 # the minimum DRAM latency (100 core cycles).  I.e. 
 #   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 16
--gpgpu_dram_return_queue_size 116
+-gpgpu_dram_return_queue_size 300
 
-# for Fermi, bus width is 384bits, this is 8 bytes (4 bytes at each DRAM chip) per memory partition
+# for Maxwell, bus width is 128bits, this is 64 bytes (32 bytes at each DRAM chip) per memory partition
 -gpgpu_n_mem_per_ctrlr 2
 -gpgpu_dram_buswidth 32
 -gpgpu_dram_burst_length 8