improving P100 accuracy

3 files changed, 9 insertions, 9 deletions

diff --git a/configs/Pascal-P100-HBM/config_fermi_islip.icnt b/configs/Pascal-P100-HBM/config_fermi_islip.icnt
index 0a73c81..e7c2c3b 100644
--- a/configs/Pascal-P100-HBM/config_fermi_islip.icnt
+++ b/configs/Pascal-P100-HBM/config_fermi_islip.icnt
@@ -17,10 +17,10 @@ routing_function = dest_tag;
 // Flow control
 
 num_vcs     = 1;
-vc_buf_size = 64;
-input_buffer_size = 64;
-ejection_buffer_size = 64;
-boundary_buffer_size = 64;
+vc_buf_size = 128;
+input_buffer_size = 256;
+ejection_buffer_size = 128;
+boundary_buffer_size = 128;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/Pascal-P100-HBM/gpgpusim.config b/configs/Pascal-P100-HBM/gpgpusim.config
index 1029194..533a865 100644
--- a/configs/Pascal-P100-HBM/gpgpusim.config
+++ b/configs/Pascal-P100-HBM/gpgpusim.config
@@ -17,7 +17,7 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Pascal NVIDIA GP100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1480.0:2960.0:1480.0:715.0
+-gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
@@ -54,7 +54,7 @@
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
 # Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  S:64:128:6,L:L:m:N:H,A:128:8,32:0,32
+-gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
 -gpgpu_shmem_size 65536
 -gmem_skip_L1D 1
 -icnt_flit_size 40
@@ -64,7 +64,7 @@
 -gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:256:4,32:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 64:64:64:64
-#-gpgpu_flush_l2_cache 1
+-perf_sim_memcpy 0
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
@@ -116,7 +116,7 @@
 # the minimum DRAM latency (100 core cycles).  I.e. 
 #   Total buffer space required = 100 x 924MHz / 700MHz = 132
 -gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 116
+-gpgpu_dram_return_queue_size 192
 
 # for HBM, 32 channles, each (128 bits) 16 bytes width
 -gpgpu_n_mem_per_ctrlr 1
diff --git a/configs/Pascal-P102-GDDR5X/gpgpusim.config b/configs/Pascal-P102-GDDR5X/gpgpusim.config
index cb69767..0c6c126 100644
--- a/configs/Pascal-P102-GDDR5X/gpgpusim.config
+++ b/configs/Pascal-P102-GDDR5X/gpgpusim.config
@@ -71,7 +71,7 @@
 -gpgpu_cache:dl2 S:64:128:16,L:B:m:F:L,A:128:4,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 1
+-perf_sim_memcpy 0
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4