diff options
| author | Mahmoud <[email protected]> | 2018-05-15 20:29:42 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-05-15 20:29:42 -0400 |
| commit | 8738aa4cde553dcf3b3315f4e7e61f1fa4faeadd (patch) | |
| tree | 98e491398476e9560e291d0b5ac085c06032a92e /configs | |
| parent | c2b43f1ff592563c1abf8bc1ac3230f2892b380a (diff) | |
fixing vache for volta
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config index c0406e9..f1ae2dc 100644 --- a/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config +++ b/configs/Nvidia-Titan-Volta/gpgpu-sim-3.x/gpgpusim.config @@ -43,10 +43,9 @@ # ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB ## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core ## we need to scale the number of pipeline registers to be equal to the number of SP units --gpgpu_pipeline_widths 4,4,4,1,4,4,4,1,12 +-gpgpu_pipeline_widths 4,4,1,4,4,1,9 -gpgpu_num_sp_units 4 -gpgpu_num_sfu_units 4 --gpgpu_num_dp_units 4 # Instruction latencies and initiation intervals # "ADD,MAX,MUL,MAD,DIV" @@ -64,25 +63,25 @@ # ** Optional parameter - Required when mshr_type==Texture Fifo # Note: Hashing set index function (H) only applies to a set size of 32 or 64. # Pascal GP100 has 64KB Shared memory --gpgpu_cache:dl1 S:64:128:8,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefL1 S:64:128:16,L:L:f:N:H,A:256:8,16:0,32 --gpgpu_cache:dl1PrefShared S:32:128:6,L:L:f:N:H,A:256:8,16:0,32 +-gpgpu_cache:dl1 64:128:8,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefL1 64:128:16,L:L:m:N:H,A:256:8,16:0 +-gpgpu_cache:dl1PrefShared 32:128:6,L:L:m:N:H,A:256:8,16:0 -gpgpu_shmem_size 65536 -gpgpu_shmem_size_PrefL1 1 -gpgpu_shmem_size_PrefShared 98304 -gmem_skip_L1D 0 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives 4.5MB L2 cache --gpgpu_cache:dl2 S:64:128:24,L:B:m:F:L,A:256:4,32:0,32 +-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32 -gpgpu_cache:dl2_texture_only 0 -gpgpu_dram_partition_queues 64:64:64:64 # 128 KB Inst. --gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4 +-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4 # 48 KB Tex --gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2 +-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2 # 64 KB Const --gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 +-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4 # enable operand collector -gpgpu_operand_collector_num_units_sp 14 |