Merge pull request #28 from abdallm/dev-purdue-integration

Dev purdue integration

10 files changed, 551 insertions, 14 deletions

diff --git a/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
new file mode 100644
index 0000000..fac792a
--- /dev/null
+++ b/configs/3.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
new file mode 100644
index 0000000..aefb04a
--- /dev/null
+++ b/configs/3.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -0,0 +1,165 @@
+# This config models the Volta Titan X
+# For more info about this card:
+# http://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf
+# https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8344474&tag=1# 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+# https://www.hotchips.org/wp-content/uploads/hc_archives/hc29/HC29.21-Monday-Pub/HC29.21.10-GPU-Gaming-Pub/HC29.21.132-Volta-Choquette-NVIDIA-Final3.pdf
+# https://devblogs.nvidia.com/inside-volta/
+# http://on-demand.gputechconf.com/gtc/2017/presentation/s7798-luke-durant-inside-volta.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 70
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 40
+-gpgpu_n_cores_per_cluster 2
+-gpgpu_n_mem 24
+-gpgpu_n_sub_partition_per_mchannel 1
+
+# volta clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA GP100  clock domains are adopted from 
+# https://en.wikipedia.org/wiki/Volta_(microarchitecture)
+-gpgpu_clock_domains 1200.0:1200.0:1200.0:850.0
+# boost mode
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,4,1,4,4,1,9
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 4
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# All Div operations are executed on SFU unit
+# Throughput (initiation latency) are adopted from 
+# http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 2,2,2,2,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,4,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Volta GV100 has 64KB Shared memory
+-gpgpu_cache:dl1  64:128:8,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefL1  64:128:16,L:L:m:N:H,A:256:8,16:0
+-gpgpu_cache:dl1PrefShared  32:128:6,L:L:m:N:H,A:256:8,16:0
+-gpgpu_shmem_size 65536
+-gpgpu_shmem_size_PrefL1 1
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 0
+
+# 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
+-gpgpu_cache:dl2 64:128:24,L:B:m:W:L,A:256:4,32:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 64:64:64:64
+
+# 128 KB Inst.
+-gpgpu_cache:il1 64:128:16,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 64 KB Const
+-gpgpu_const_cache:l1 128:64:8,L:R:f:N:L,A:2:64,4
+
+# enable operand collector
+-gpgpu_operand_collector_num_units_sp 14
+-gpgpu_operand_collector_num_units_sfu 8
+-gpgpu_operand_collector_num_units_mem 10
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 1
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for HBM, 32 channles, each (128 bits) 16 bytes width
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 16
+-gpgpu_dram_burst_length 2
+-dram_data_command_freq_ratio 2  # HBM is DDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
+
+# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
+# Timing for 1 GHZ
+# tRRDl and tWTR are missing, need to be added
+#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
+#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
+
+# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
+-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
+                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 0
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index c96432b..05663c2 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -57,6 +57,7 @@
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 35
 -smem_latency 26
+-gpgpu_flush_l1_cache 1
 
 # The alternative configuration for fermi in case cudaFuncCachePreferL1 is selected
 #-gpgpu_cache:dl1  N:64:128:6,L:L:m:N:H,S:64:8,8
@@ -66,7 +67,7 @@
 -gpgpu_cache:dl2 S:64:128:8,L:B:m:L:L,A:256:4,4:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
+-perf_sim_memcpy 1
 -memory_partition_indexing 0
 
 -gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
diff --git a/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt b/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
new file mode 100644
index 0000000..85ac0d7
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX/1Xintes.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 64;
+input_buffer_size = 256;
+ejection_buffer_size = 64;
+boundary_buffer_size = 64;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt b/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
new file mode 100644
index 0000000..d4e3467
--- /dev/null
+++ b/configs/4.x-cfgs/SM6_TITANX/1Xintes_LB.icnt
@@ -0,0 +1,73 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 45a87cd..1b4e6e3 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -71,21 +71,25 @@
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
+# By default, L1 cache is disabled in Pascal P102.
+# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1
 -gmem_skip_L1D 1
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 82
 -smem_latency 24
+-gpgpu_flush_l1_cache 1
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
 -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
--perf_sim_memcpy 0
+-perf_sim_memcpy 1
 
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
 # 48 KB Tex 
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
diff --git a/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt b/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
new file mode 100644
index 0000000..fca9ffe
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/1Xintes.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 256;
+input_buffer_size = 256;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt b/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
new file mode 100644
index 0000000..c6badd3
--- /dev/null
+++ b/configs/4.x-cfgs/SM7_TITANV/1Xintes_LB.icnt
@@ -0,0 +1,74 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 40; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 64;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 32;
+input_buffer_size = 32;
+ejection_buffer_size = 32;
+boundary_buffer_size = 32;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 1;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
index cea3acf..2f25889 100644
--- a/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
+++ b/configs/4.x-cfgs/SM7_TITANV/config_fermi_islip.icnt
@@ -20,8 +20,8 @@ routing_function = dest_tag;
 num_vcs     = 1;
 vc_buf_size = 256;
 input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
+ejection_buffer_size = 256;
+boundary_buffer_size = 256;
 
 wait_for_tail_credit = 0;
 
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index 14faedb..6fe441b 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -27,9 +27,9 @@
 #-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
 # Volta NVIDIA GV100  clock domains are adopted from 
 # https://en.wikipedia.org/wiki/Volta_(microarchitecture)
--gpgpu_clock_domains 1200.0:1200.0:2000.0:850.0
+-gpgpu_clock_domains 1200.0:2000.0:1200.0:850.0
 # boost mode
-# -gpgpu_clock_domains 1455.0:1455.0:2000.0:850.0
+# -gpgpu_clock_domains 1455.0:2000.0:1455.0:850.0
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
@@ -65,18 +65,20 @@
 
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
-# Defualt config is 64KB DL1 and 64KB shared memory
--gpgpu_cache:dl1  S:4:128:128,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:4:128:192,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 32768
--gpgpu_shmem_size_PrefShared 98304
+# Defualt config is 32KB DL1 and 96KB shared memory
+# In Volta, we assign the remaining shared memory to L1 cache 
+# if the assigned shd mem = 0, then L1 cache = 128KB
+# For more info, see https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#shared-memory-7-x 
+# disable this mode in case of multi kernels/apps execution
+-adpative_volta_cache_config 1
+-gpgpu_cache:dl1  S:4:128:64,L:L:s:N:L,A:256:8,16:0,32
+-gpgpu_shmem_size 98304
 -gmem_skip_L1D 0
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
 -l1_latency 28
 -smem_latency 19
+-gpgpu_flush_l1_cache 1
 
 # 64 sets, each 128 bytes 24-way for each memory sub partition (192 KB per memory sub partition). This gives  4.5MB L2 cache
 -gpgpu_cache:dl2 S:64:128:24,L:B:m:L:L,A:384:4,32:0,32
@@ -86,7 +88,8 @@
 
 # 128 KB Inst.
 -gpgpu_cache:il1 N:64:128:16,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
+# 48 KB Tex
+# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod
 -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 64 KB Const
 -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4