diff options
| author | Mahmoud <[email protected]> | 2019-05-02 15:49:03 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2019-05-02 15:49:03 -0400 |
| commit | ad37c917f8641930f9f58c3f04fa6e22600015cd (patch) | |
| tree | bf5d50e0b342201e63b21ddf6d7b665bd8a3b4f1 /configs | |
| parent | bbef52a122761bc8f02092e0acf867dbd87cbe70 (diff) | |
fixing some typos in config files
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 4 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 13d8c8f..f454240 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -53,7 +53,7 @@ # Pipeline widths and number of FUs # ID_OC_SP,ID_OC_DP,ID_OC_INT,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_INT,OC_EX_SFU,OC_EX_MEM,EX_WB,ID_OC_TENSOR_CORE,OC_EX_TENSOR_CORE -## Volta TITANV has 4 SP SIMD units, 4 SFU units, 4 DP units per core, 4 Tensor core units +## Volta TITANV has 4 SP SIMD units, 4 INT units, 4 SFU units, 4 DP units per core, 4 Tensor core units ## we need to scale the number of pipeline registers to be equal to the number of SP units -gpgpu_pipeline_widths 4,4,4,4,4,4,4,4,4,4,8,4,4 -gpgpu_num_sp_units 4 @@ -113,7 +113,7 @@ # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -# Volta has sub core model, in which each scheduler has its own reisiter file and EUs +# Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated -sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead diff --git a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config index 3e4a8fa..b1ce11c 100644 --- a/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV_fastlocalxbar/gpgpusim.config @@ -102,9 +102,9 @@ # 64 KB Const -gpgpu_const_cache:l1 N:128:64:8,L:R:f:N:L,S:2:64,4 -# Volta has sub core model, in which each scheduler has its own reisiter file and EUs +# Volta has sub core model, in which each scheduler has its own register file and EUs # i.e. schedulers are isolated --sub_core_model 0 +-sub_core_model 1 # disable specialized operand collectors and use generic operand collectors instead -enable_specialized_operand_collector 0 -gpgpu_operand_collector_num_units_gen 8 |