Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/TimRogersGroup/gpgpu-sim_distribution into dev-purdue-integration

11 files changed, 239 insertions, 1 deletions

diff --git a/configs/3.x-cfgs/GTX480/gpgpusim.config b/configs/3.x-cfgs/GTX480/gpgpusim.config
index 436cb41..ee90c12 100644
--- a/configs/3.x-cfgs/GTX480/gpgpusim.config
+++ b/configs/3.x-cfgs/GTX480/gpgpusim.config
@@ -22,6 +22,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
 
 # This implies a maximum of 48 warps/SM
 -gpgpu_shader_core_pipeline 1536:32 
diff --git a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
index 8b030b6..c675aab 100644
--- a/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
+++ b/configs/3.x-cfgs/GeForceGTX750Ti/gpgpusim.config
@@ -21,6 +21,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 52
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
diff --git a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
index cb87b65..6f836ee 100644
--- a/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
+++ b/configs/3.x-cfgs/QuadroFX5600/gpgpusim.config
@@ -11,6 +11,9 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 12
+
+-gpgpu_occupancy_sm_number 12
 #8192 (registers per block as written by device Query and which used in this option in our other configurations but this break some benchmarks execution! it does not affect performance modeling though)
 -gpgpu_shader_core_pipeline 768:32 
 -gpgpu_shader_cta 8
diff --git a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
index 82243c2..fef1110 100644
--- a/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
+++ b/configs/3.x-cfgs/QuadroFX5800/gpgpusim.config
@@ -11,6 +11,8 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 16384
+-gpgpu_occupancy_sm_number 13
+
 -gpgpu_shader_core_pipeline 1024:32 
 -gpgpu_shader_cta 8
 -gpgpu_simd_model 1
diff --git a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
index 47c2b6a..fb044c6 100644
--- a/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
+++ b/configs/3.x-cfgs/SM6_GTX1080/gpgpusim.config
@@ -3,7 +3,7 @@
 # functional simulator specification
 -gpgpu_ptx_instruction_classification 0
 -gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 20 
+-gpgpu_ptx_force_max_capability 60
 
 # SASS execution (only supported with CUDA >= 4.0)
 -gpgpu_ptx_convert_to_ptxplus 0
@@ -23,6 +23,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 60
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
diff --git a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
index 442ab8b..6ac2c12 100644
--- a/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
+++ b/configs/3.x-cfgs/TeslaC2050/gpgpusim.config
@@ -25,6 +25,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
 
 # This implies a maximum of 48 warps/SM
 -gpgpu_shader_core_pipeline 1536:32 
diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 05663c2..4096b09 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -22,6 +22,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 20
 
 # This implies a maximum of 48 warps/SM
 -gpgpu_shader_core_pipeline 1536:32 
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 1b4e6e3..3842508 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -27,6 +27,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 32768
+-gpgpu_occupancy_sm_number 62
 
 # This implies a maximum of 32 warps/SM
 -gpgpu_shader_core_pipeline 1024:32 
diff --git a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
index 6fe441b..c8351da 100644
--- a/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/4.x-cfgs/SM7_TITANV/gpgpusim.config
@@ -33,6 +33,7 @@
 
 # shader core pipeline config
 -gpgpu_shader_registers 65536
+-gpgpu_occupancy_sm_number 70
 
 # This implies a maximum of 64 warps/SM
 -gpgpu_shader_core_pipeline 2048:32 
diff --git a/configs/Pascal_TITANX/config_fermi_islip.icnt b/configs/Pascal_TITANX/config_fermi_islip.icnt
new file mode 100644
index 0000000..602daee
--- /dev/null
+++ b/configs/Pascal_TITANX/config_fermi_islip.icnt
@@ -0,0 +1,70 @@
+//21*1 fly with 32 flits per packet under gpgpusim injection mode
+use_map = 0;
+flit_size = 32; 
+
+// currently we do not use this, see subnets below
+network_count = 2;
+
+// Topology
+topology = fly;
+k = 52;
+n = 1;
+
+// Routing
+
+routing_function = dest_tag;
+
+// Flow control
+
+num_vcs     = 1;
+vc_buf_size = 8;
+
+wait_for_tail_credit = 0;
+
+// Router architecture
+
+vc_allocator = islip; //separable_input_first;
+sw_allocator = islip; //separable_input_first;
+alloc_iters  = 1;
+
+credit_delay   = 0;
+routing_delay  = 0;
+vc_alloc_delay = 1;
+sw_alloc_delay = 1;
+
+input_speedup     = 2;
+output_speedup    = 1;
+internal_speedup  = 1.0;
+
+// Traffic, GPGPU-Sim does not use this
+
+traffic                = uniform;
+packet_size ={{1,2,3,4},{10,20}};
+packet_size_rate={{1,1,1,1},{2,1}};
+
+// Simulation - Don't change
+
+sim_type       = gpgpusim;
+//sim_type = latency;
+injection_rate = 0.1;
+
+subnets = 2;
+
+// Always use read and write no matter following line
+//use_read_write = 1;
+
+
+read_request_subnet = 0;
+read_reply_subnet = 1;
+write_request_subnet = 0;
+write_reply_subnet = 1;
+
+read_request_begin_vc = 0;
+read_request_end_vc = 0;
+write_request_begin_vc = 0;
+write_request_end_vc = 0;
+read_reply_begin_vc = 0;
+read_reply_end_vc = 0;
+write_reply_begin_vc = 0;
+write_reply_end_vc = 0;
+
diff --git a/configs/Pascal_TITANX/gpgpusim.config b/configs/Pascal_TITANX/gpgpusim.config
new file mode 100644
index 0000000..f78bd02
--- /dev/null
+++ b/configs/Pascal_TITANX/gpgpusim.config
@@ -0,0 +1,156 @@
+# This config models the Pascal GP102 (NVIDIA TITAN X)
+# For more info about this card, see Nvidia White paper
+# http://international.download.nvidia.com/geforce-com/international/pdfs/GeForce_GTX_1080_Whitepaper_FINAL.pdf
+
+# functional simulator specification
+-gpgpu_ptx_instruction_classification 0
+-gpgpu_ptx_sim_mode 0
+-gpgpu_ptx_force_max_capability 61
+
+# SASS execution (only supported with CUDA >= 4.0)
+-gpgpu_ptx_convert_to_ptxplus 0
+-gpgpu_ptx_save_converted_ptxplus 0
+
+# high level architecture configuration
+-gpgpu_n_clusters 28
+-gpgpu_n_cores_per_cluster 1
+-gpgpu_n_mem 12
+-gpgpu_n_sub_partition_per_mchannel 2 
+
+# Pascal clock domains
+#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
+# Pascal NVIDIA TITAN X clock domains are adopted from 
+# https://en.wikipedia.org/wiki/GeForce_10_series
+-gpgpu_clock_domains 1417.0:1417.0:1417.0:2500.0
+
+# shader core pipeline config
+-gpgpu_shader_registers 65536
+
+# This implies a maximum of 64 warps/SM
+-gpgpu_shader_core_pipeline 2048:32 
+-gpgpu_shader_cta 32
+-gpgpu_simd_model 1 
+
+# Pipeline widths and number of FUs
+# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
+## Pascal GP102 has 4 SP SIMD units and 1 SFU unit
+## we need to scale the number of pipeline registers to be equal to the number of SP units
+-gpgpu_pipeline_widths 4,1,1,4,1,1,6
+-gpgpu_num_sp_units 4
+-gpgpu_num_sfu_units 1
+
+# Instruction latencies and initiation intervals
+# "ADD,MAX,MUL,MAD,DIV"
+# SFU is 32-width in pascal, then dp units initiation is 1 cycle
+-ptx_opcode_latency_int 4,13,4,5,145
+-ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_fp 4,13,4,5,39
+-ptx_opcode_initiation_fp 1,2,1,1,4
+-ptx_opcode_latency_dp 8,19,8,8,330
+-ptx_opcode_initiation_dp 4,8,4,4,130
+
+# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
+# ** Optional parameter - Required when mshr_type==Texture Fifo
+# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
+# Pascal GP102 has 96KB Shared memory
+# Pascal GP102 has 64KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres is used
+-gpgpu_cache:dl1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefL1  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_cache:dl1PrefShared  64:128:6,L:L:m:N:H,A:128:8,16
+-gpgpu_shmem_size 98304
+-gpgpu_shmem_size_PrefL1 98304
+-gpgpu_shmem_size_PrefShared 98304
+-gmem_skip_L1D 1
+
+# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
+-gpgpu_cache:dl2 64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2_texture_only 0 
+-gpgpu_dram_partition_queues 32:32:32:32
+
+# 4 KB Inst.
+-gpgpu_cache:il1 8:128:4,L:R:f:N:L,A:2:48,4
+# 48 KB Tex 
+-gpgpu_tex_cache:l1 16:128:24,L:R:m:N:L,F:128:4,128:2
+# 12 KB Const
+-gpgpu_const_cache:l1 128:64:2,L:R:f:N:L,A:2:64,4
+
+# enable operand collector 
+## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units
+-gpgpu_operand_collector_num_units_sp 20
+-gpgpu_operand_collector_num_units_sfu 4
+-gpgpu_operand_collector_num_units_mem 8
+-gpgpu_operand_collector_num_in_ports_sp 4
+-gpgpu_operand_collector_num_out_ports_sp 4
+-gpgpu_operand_collector_num_in_ports_sfu 1
+-gpgpu_operand_collector_num_out_ports_sfu 1
+-gpgpu_operand_collector_num_in_ports_mem 1
+-gpgpu_operand_collector_num_out_ports_mem 1
+# gpgpu_num_reg_banks should be increased to 32
+-gpgpu_num_reg_banks 32
+
+# shared memory bankconflict detection 
+-gpgpu_shmem_num_banks 32
+-gpgpu_shmem_limited_broadcast 0
+-gpgpu_shmem_warp_parts 1
+
+## In Pascal, a warp scheduler can issue 2 insts per cycle
+-gpgpu_max_insn_issue_per_warp 2
+
+# interconnection
+-network_mode 1 
+-inter_config_file config_fermi_islip.icnt
+
+# memory partition latency config 
+-rop_latency 120
+-dram_latency 100
+
+# dram model config
+-gpgpu_dram_scheduler 1
+# The DRAM return queue and the scheduler queue together should provide buffer
+# to sustain the memory level parallelism to tolerate DRAM latency 
+# To allow 100% DRAM utility, there should at least be enough buffer to sustain
+# the minimum DRAM latency (100 core cycles).  I.e. 
+#   Total buffer space required = 100 x 924MHz / 700MHz = 132
+-gpgpu_frfcfs_dram_sched_queue_size 64
+-gpgpu_dram_return_queue_size 116
+
+# for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)
+# 12 memory paritions, 4 bytes (1 DRAM chip) per memory partition
+# the atom size of GDDR5X (the smallest read request) is 32 bytes 
+-gpgpu_n_mem_per_ctrlr 1
+-gpgpu_dram_buswidth 4
+-gpgpu_dram_burst_length 8
+-dram_data_command_freq_ratio 4  # GDDR5X is QDR
+-gpgpu_mem_address_mask 1
+-gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS
+
+# Use the same GDDR5 timing from hynix H5GQ1H24AFR
+# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0
+-gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=6:RCD=12:RAS=28:RP=12:RC=40:
+                        CL=12:WL=4:CDLR=5:WR=12:nbkgrp=1:CCDL=0:RTPL=0"
+
+# Fermi has two schedulers per core
+-gpgpu_num_sched_per_core 4
+# Two Level Scheduler with active and pending pools
+#-gpgpu_scheduler two_level_active:6:0:1
+# Loose round robbin scheduler
+#-gpgpu_scheduler lrr
+# Greedy then oldest scheduler
+-gpgpu_scheduler gto
+
+# stat collection
+-gpgpu_memlatency_stat 14 
+-gpgpu_runtime_stat 500
+-enable_ptx_file_line_stats 1
+-visualizer_enabled 0
+
+# power model configs
+-power_simulation_enabled 1
+-gpuwattch_xml_file gpuwattch_gtx480.xml
+
+# tracing functionality
+#-trace_enabled 1
+#-trace_components WARP_SCHEDULER,SCOREBOARD
+#-trace_sampling_core 0
+