Merge remote-tracking branch 'localpub/dev' into dev

4 files changed, 12 insertions, 12 deletions

diff --git a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
index 4a7a3c3..6f088ea 100644
--- a/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/tested-cfgs/SM2_GTX480/gpgpusim.config
@@ -46,9 +46,9 @@
 -gpgpu_num_dp_units 0
 
 # Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,2,2,1,8
+# "ADD,MAX,MUL,MAD,DIV,SHFL"
+-ptx_opcode_latency_int 4,13,4,5,145,32
+-ptx_opcode_initiation_int 1,2,2,1,8,4
 -ptx_opcode_latency_fp 4,13,4,5,39
 -ptx_opcode_initiation_fp 1,2,1,1,4
 -ptx_opcode_latency_dp 8,19,8,8,330
diff --git a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
index e6d8f1d..391269e 100644
--- a/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/tested-cfgs/SM6_TITANX/gpgpusim.config
@@ -56,11 +56,11 @@
 
 
 # Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
+# "ADD,MAX,MUL,MAD,DIV,SHFL"
 # All Div operations are executed on SFU unit
 # Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
+-ptx_opcode_latency_int 4,13,4,5,145,32
+-ptx_opcode_initiation_int 1,1,1,1,4,4
 -ptx_opcode_latency_fp 4,13,4,5,39
 -ptx_opcode_initiation_fp 1,2,1,1,4
 -ptx_opcode_latency_dp 8,19,8,8,330
@@ -136,7 +136,7 @@
 
 # interconnection
 -network_mode 1 
--inter_config_file config_fermi_islip.icnt
+-inter_config_file config_pascal_islip.icnt
 
 # memory partition latency config 
 -rop_latency 120
diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
index 23a57fa..91ff0b4 100644
--- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config
@@ -69,8 +69,8 @@
 # All Div operations are executed on SFU unit
 # Throughput (initiation latency) are adopted from 
 # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_int 4,13,4,5,145,21
+-ptx_opcode_initiation_int 2,2,2,2,8,4
 -ptx_opcode_latency_fp 4,13,4,5,39
 -ptx_opcode_initiation_fp 2,2,2,2,4
 -ptx_opcode_latency_dp 8,19,8,8,330
diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
index 0339b0d..a77ab74 100644
--- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
+++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config
@@ -67,10 +67,10 @@
 # Instruction latencies and initiation intervals
 # "ADD,MAX,MUL,MAD,DIV"
 # All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from 
+# Throughput (initiation latency except shfl) are adopted from 
 # http://on-demand.gputechconf.com/gtc/2018/presentation/s8122-dissecting-the-volta-gpu-architecture-through-microbenchmarking.pdf
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 2,2,2,2,8
+-ptx_opcode_latency_int 4,13,4,5,145,32
+-ptx_opcode_initiation_int 2,2,2,2,8,4
 -ptx_opcode_latency_fp 4,13,4,5,39
 -ptx_opcode_initiation_fp 2,2,2,2,4
 -ptx_opcode_latency_dp 8,19,8,8,330