diff options
| author | Wilson Fung <[email protected]> | 2012-10-30 22:43:44 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:49:21 -0700 |
| commit | d0b377ded0c804580a78f2327b84e6e2ea1ee069 (patch) | |
| tree | cc14f8b6a599b86e5da351c66eee5ab40962da56 /configs | |
| parent | 3863ad27814eefe2d26b2eba7eb8a4ab65bef5a4 (diff) | |
Fixed the shared memory bank conflict model for GTX 480 and Tesla C2050. Now the two configs will feature 32-bank shared memory with a more flexible broadcast mechanism.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14509]
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/GTX480/gpgpusim.config | 25 | ||||
| -rw-r--r-- | configs/TeslaC2050/gpgpusim.config | 31 |
2 files changed, 32 insertions, 24 deletions
diff --git a/configs/GTX480/gpgpusim.config b/configs/GTX480/gpgpusim.config index fd23e57..abd9627 100644 --- a/configs/GTX480/gpgpusim.config +++ b/configs/GTX480/gpgpusim.config @@ -3,6 +3,11 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 20 + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + # high level architecture configuration -gpgpu_n_clusters 15 -gpgpu_n_cores_per_cluster 1 @@ -37,6 +42,7 @@ -ptx_opcode_latency_dp 8,19,8,8,330 -ptx_opcode_initiation_dp 8,16,8,8,130 + # In Fermi, the cache and shared memory can be configured to 16kb:48kb(default) or 48kb:16kb # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry> # ** Optional parameter - Required when mshr_type==Texture Fifo @@ -55,8 +61,16 @@ -gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2 -gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4 +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 -gpgpu_num_reg_banks 16 +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 -gpgpu_max_insn_issue_per_warp 1 @@ -97,14 +111,5 @@ -gpgpu_memlatency_stat 14 -gpgpu_runtime_stat 500 -enable_ptx_file_line_stats 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 -visualizer_enabled 0 + diff --git a/configs/TeslaC2050/gpgpusim.config b/configs/TeslaC2050/gpgpusim.config index 86f0d85..4871378 100644 --- a/configs/TeslaC2050/gpgpusim.config +++ b/configs/TeslaC2050/gpgpusim.config @@ -3,6 +3,14 @@ -gpgpu_ptx_sim_mode 0 -gpgpu_ptx_force_max_capability 20 +# Using cuobjdump to extract ptx/SASS +#-gpgpu_ptx_use_cuobjdump 1 # use default + +# SASS execution (only supported with CUDA >= 4.0) +-gpgpu_ptx_convert_to_ptxplus 0 +-gpgpu_ptx_save_converted_ptxplus 0 + + # high level architecture configuration -gpgpu_n_clusters 14 -gpgpu_n_cores_per_cluster 1 @@ -56,8 +64,16 @@ -gpgpu_tex_cache:l1 4:128:24,L:R:m:N,F:128:4,128:2 -gpgpu_const_cache:l1 64:64:2,L:R:f:N,A:2:32,4 +# enable operand collector +-gpgpu_operand_collector_num_units_sp 6 +-gpgpu_operand_collector_num_units_sfu 8 +-gpgpu_operand_collector_num_in_ports_sp 2 +-gpgpu_operand_collector_num_out_ports_sp 2 -gpgpu_num_reg_banks 16 +# shared memory bankconflict detection +-gpgpu_shmem_num_banks 32 +-gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 -gpgpu_max_insn_issue_per_warp 1 @@ -98,18 +114,5 @@ -gpgpu_memlatency_stat 14 -gpgpu_runtime_stat 500 -enable_ptx_file_line_stats 1 - -# Using cuobjdump to extract ptx/SASS --gpgpu_ptx_use_cuobjdump 1 - -# SASS execution (only supported with CUDA >= 4.0) --gpgpu_ptx_convert_to_ptxplus 0 --gpgpu_ptx_save_converted_ptxplus 0 - -# enable operand collector --gpgpu_operand_collector_num_units_sp 6 --gpgpu_operand_collector_num_units_sfu 8 --gpgpu_operand_collector_num_in_ports_sp 2 --gpgpu_operand_collector_num_out_ports_sp 2 -visualizer_enabled 0 --keep 1 + |