diff options
| author | Mahmoud <[email protected]> | 2018-09-18 10:52:10 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-09-18 10:52:10 -0400 |
| commit | dd0a4eef2ae526984ac3e7dc93a0d1cf92a9a6a8 (patch) | |
| tree | 06466a648401b1632f002dc1cca4963d0cb867a6 /configs | |
| parent | 950e981534a9e0fb057b11b5ae8d86598f8953d0 (diff) | |
removing some comments from config files
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config index 9ea7202..4c0586d 100644 --- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -109,7 +109,7 @@ -gpgpu_shmem_num_banks 32 -gpgpu_shmem_limited_broadcast 0 -gpgpu_shmem_warp_parts 1 -# Use Fermi Coalsce arhitetecture which is the same as Pascal +# Use Pascal Coalsce arhitetecture -gpgpu_coalesce_arch 61 ## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units @@ -144,8 +144,7 @@ -gpgpu_mem_address_mask 1 -gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBCCCC.BCCSSSSS -# Use the same GDDR5 timing from hynix H5GQ1H24AFR -# disable bank groups for now, set nbkgrp to 1 and tCCDL and tRTPL to 0 +# Use the same GDDR5 timing -gpgpu_dram_timing_opt "nbk=16:CCD=2:RRD=8:RCD=16:RAS=37:RP=16:RC=52: CL=16:WL=6:CDLR=7:WR=16:nbkgrp=4:CCDL=4:RTPL=3" |