diff options
| author | Mahmoud <[email protected]> | 2018-10-10 17:48:52 -0400 |
|---|---|---|
| committer | Mahmoud <[email protected]> | 2018-10-10 17:48:52 -0400 |
| commit | dff0779550852ea3eba72c8b113feb3c4978823f (patch) | |
| tree | ae39788fe381f9392e7d544d39b35206aeff7964 /configs | |
| parent | 0e46a261dfeba9c19d1637f46277986d7eb1b9d8 (diff) | |
adding some comment to config files
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/4.x-cfgs/SM6_TITANX/gpgpusim.config | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config index 3723163..cc7419c 100644 --- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config +++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config @@ -71,6 +71,8 @@ -gpgpu_shmem_size 49152 -gpgpu_shmem_size_PrefL1 49152 -gpgpu_shmem_size_PrefShared 49152 +# By default, L1 cache is disabled in Pascal P102. +# requests with .nc modifier or __ldg mehtod will be cached in L1 cache even with gmem_skip_L1D=1 -gmem_skip_L1D 1 -icnt_flit_size 40 -gpgpu_n_cluster_ejection_buffer_size 32 @@ -87,6 +89,7 @@ # 4 KB Inst. -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4 # 48 KB Tex +# Note, TEX is deprected in Volta, It is used for legacy apps only. Use L1D cache instead with .nc modifier or __ldg mehtod -gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2 # 12 KB Const -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4 |