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authorMahmoud <[email protected]>2017-10-31 21:48:14 -0400
committerMahmoud <[email protected]>2017-10-31 21:48:14 -0400
commitf1d2d4ecb28a17fd44da5c1a282767986cdb0d94 (patch)
tree7d3f426d84c4485792ef0d3b616fc437ad74b566 /configs
parent121b2b898261fb775144f660bf9fcfb041b0a0f9 (diff)
parent4df2f7d2499600fa0f0c5642c07fed6576aa5713 (diff)
Merge branch 'dev-purdue-integration' of https://github.rcac.purdue.edu/abdallm/gpgpu-sim_distribution into dev-purdue-integration
Diffstat (limited to 'configs')
-rw-r--r--configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config6
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
index 82dfa9a..4191eb0 100644
--- a/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
+++ b/configs/PascalTitanX/gpgpu-sim-3.x/gpgpusim.config
@@ -64,16 +64,16 @@
-gmem_skip_L1D 1
# 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:W:L,A:128:8,4:0,32
+-gpgpu_cache:dl2 N:64:128:16,L:B:m:W:L,A:128:8,4:0,32
-gpgpu_cache:dl2_texture_only 0
-gpgpu_dram_partition_queues 32:32:32:32
# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
+-gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,A:2:48,4
# 48 KB Tex
-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
+-gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,A:2:64,4
# enable operand collector
## larger operand collectors and reg_banks are needed for the 4 warp schedulers and 4 SIMD units