diff options
| author | JRPAN <[email protected]> | 2021-05-17 17:35:06 -0400 |
|---|---|---|
| committer | JRPAN <[email protected]> | 2021-05-18 19:54:39 -0400 |
| commit | f7833519471ce92619bd1e4807ec07eb55aed76e (patch) | |
| tree | 0a6a5a3cc523ff02c22142be667e1155a8e49487 /configs | |
| parent | 585dcf5dc05d6343314600114ebcea8c719e7423 (diff) | |
new configs - adaptive cache and cache write ratio
Diffstat (limited to 'configs')
| -rw-r--r-- | configs/tested-cfgs/SM75_RTX2060/gpgpusim.config | 2 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_QV100/gpgpusim.config | 6 | ||||
| -rw-r--r-- | configs/tested-cfgs/SM7_TITANV/gpgpusim.config | 3 |
3 files changed, 11 insertions, 0 deletions
diff --git a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config index 6189dca..e006085 100644 --- a/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config +++ b/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config @@ -110,6 +110,8 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_shmem_option 0,8,16,32,64,100 +-gpgpu_unified_l1d_size 128 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives us 3MB L2 cache -gpgpu_cache:dl2 S:64:128:16,L:B:m:L:P,A:192:4,32:0,32 diff --git a/configs/tested-cfgs/SM7_QV100/gpgpusim.config b/configs/tested-cfgs/SM7_QV100/gpgpusim.config index bc5677c..043fce6 100644 --- a/configs/tested-cfgs/SM7_QV100/gpgpusim.config +++ b/configs/tested-cfgs/SM7_QV100/gpgpusim.config @@ -124,6 +124,9 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 6MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 @@ -203,3 +206,6 @@ #-trace_components WARP_SCHEDULER,SCOREBOARD #-trace_sampling_core 0 +-gpgpu_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128
\ No newline at end of file diff --git a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config index 3fa51ee..1f0c15f 100644 --- a/configs/tested-cfgs/SM7_TITANV/gpgpusim.config +++ b/configs/tested-cfgs/SM7_TITANV/gpgpusim.config @@ -125,6 +125,9 @@ -gpgpu_l1_latency 20 -gpgpu_smem_latency 20 -gpgpu_flush_l1_cache 1 +-gpgpu_cache_write_ratio 25 +-gpgpu_shmem_option 0,12,24,48,96 +-gpgpu_unified_l1d_size 128 # 32 sets, each 128 bytes 24-way for each memory sub partition (96 KB per memory sub partition). This gives us 4.5MB L2 cache -gpgpu_cache:dl2 S:32:128:24,L:B:m:L:P,A:192:4,32:0,32 |