adding streamin cache + fixing TEX cache + adding l1 latency and smem latency

6 files changed, 16 insertions, 507 deletions

diff --git a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
index 7f8da49..35341f7 100644
--- a/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
+++ b/configs/4.x-cfgs/SM2_GTX480/gpgpusim.config
@@ -67,7 +67,7 @@
 -memory_partition_indexing 0
 
 -gpgpu_cache:il1 N:4:128:4,L:R:f:N:L,S:2:32,4
--gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 N:4:128:24,L:R:m:N:L,T:128:4,128:2
 -gpgpu_const_cache:l1 N:64:64:2,L:R:f:N:L,S:2:32,4
 
 # enable operand collector 
diff --git a/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt
deleted file mode 100644
index e7c2c3b..0000000
--- a/configs/4.x-cfgs/SM6_P100/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 60;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 128;
-input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_P100/gpgpusim.config b/configs/4.x-cfgs/SM6_P100/gpgpusim.config
deleted file mode 100644
index a4e745d..0000000
--- a/configs/4.x-cfgs/SM6_P100/gpgpusim.config
+++ /dev/null
@@ -1,174 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 28
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# Pscal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 2
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 2,2,2,2,130
--ptx_opcode_latency_sfu 8
--ptx_opcode_initiation_sfu 4
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 65536
--gpgpu_shmem_size_PrefShared 65536
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
-
-# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
--memory_partition_indexing 2
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt b/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
deleted file mode 100644
index 81153b0..0000000
--- a/configs/4.x-cfgs/SM6_P100_64SMs/config_fermi_islip.icnt
+++ /dev/null
@@ -1,73 +0,0 @@
-//21*1 fly with 32 flits per packet under gpgpusim injection mode
-use_map = 0;
-flit_size = 40; 
-
-// currently we do not use this, see subnets below
-network_count = 2;
-
-// Topology
-topology = fly;
-k = 64;
-n = 1;
-
-// Routing
-
-routing_function = dest_tag;
-
-// Flow control
-
-num_vcs     = 1;
-vc_buf_size = 128;
-input_buffer_size = 256;
-ejection_buffer_size = 128;
-boundary_buffer_size = 128;
-
-wait_for_tail_credit = 0;
-
-// Router architecture
-
-vc_allocator = islip; //separable_input_first;
-sw_allocator = islip; //separable_input_first;
-alloc_iters  = 1;
-
-credit_delay   = 0;
-routing_delay  = 0;
-vc_alloc_delay = 1;
-sw_alloc_delay = 1;
-
-input_speedup     = 2;
-output_speedup    = 1;
-internal_speedup  = 1.0;
-
-// Traffic, GPGPU-Sim does not use this
-
-traffic                = uniform;
-packet_size ={{1,2,3,4},{10,20}};
-packet_size_rate={{1,1,1,1},{2,1}};
-
-// Simulation - Don't change
-
-sim_type       = gpgpusim;
-//sim_type = latency;
-injection_rate = 0.1;
-
-subnets = 2;
-
-// Always use read and write no matter following line
-//use_read_write = 1;
-
-
-read_request_subnet = 0;
-read_reply_subnet = 1;
-write_request_subnet = 0;
-write_reply_subnet = 1;
-
-read_request_begin_vc = 0;
-read_request_end_vc = 0;
-write_request_begin_vc = 0;
-write_request_end_vc = 0;
-read_reply_begin_vc = 0;
-read_reply_end_vc = 0;
-write_reply_begin_vc = 0;
-write_reply_end_vc = 0;
-
diff --git a/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config b/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
deleted file mode 100644
index edcd919..0000000
--- a/configs/4.x-cfgs/SM6_P100_64SMs/gpgpusim.config
+++ /dev/null
@@ -1,174 +0,0 @@
-# functional simulator specification
--gpgpu_ptx_instruction_classification 0
--gpgpu_ptx_sim_mode 0
--gpgpu_ptx_force_max_capability 60 
-
-# SASS execution (only supported with CUDA >= 4.0)
--gpgpu_ptx_convert_to_ptxplus 0
--gpgpu_ptx_save_converted_ptxplus 0
-
-# high level architecture configuration
--gpgpu_n_clusters 32
--gpgpu_n_cores_per_cluster 2
--gpgpu_n_mem 32
--gpgpu_n_sub_partition_per_mchannel 1 
-
-# Pscal clock domains
-#-gpgpu_clock_domains <Core Clock>:<Interconnect Clock>:<L2 Clock>:<DRAM Clock>
-# Pascal NVIDIA GP100  clock domains are adopted from 
-# https://en.wikipedia.org/wiki/Nvidia_Tesla
--gpgpu_clock_domains 1480.0:1480.0:1480.0:715.0
-
-# shader core pipeline config
--gpgpu_shader_registers 65536
-
-# This implies a maximum of 64 warps/SM
--gpgpu_shader_core_pipeline 2048:32 
--gpgpu_shader_cta 32
--gpgpu_simd_model 1 
-
-# Pipeline widths and number of FUs
-# ID_OC_SP,ID_OC_DP,ID_OC_SFU,ID_OC_MEM,OC_EX_SP,OC_EX_DP,OC_EX_SFU,OC_EX_MEM,EX_WB
-## Pascal GP100 has 2 SP SIMD units, 2 SFU units, 2 DP units per core
-## we need to scale the number of pipeline registers to be equal to the number of SP units
--gpgpu_pipeline_widths 2,2,2,1,2,2,2,1,6
--gpgpu_num_sp_units 2
--gpgpu_num_sfu_units 2
--gpgpu_num_dp_units 2
-
-# Instruction latencies and initiation intervals
-# "ADD,MAX,MUL,MAD,DIV"
-# All Div operations are executed on SFU unit
-# Throughput (initiation latency) are adopted from CUDA SDK document V8, section 5.4.1, Table 2
--ptx_opcode_latency_int 4,13,4,5,145
--ptx_opcode_initiation_int 1,1,1,1,4
--ptx_opcode_latency_fp 4,13,4,5,39
--ptx_opcode_initiation_fp 1,2,1,1,4
--ptx_opcode_latency_dp 8,19,8,8,330
--ptx_opcode_initiation_dp 2,2,2,2,130
--ptx_opcode_latency_sfu 8
--ptx_opcode_initiation_sfu 4
-
-
-# <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
-# ** Optional parameter - Required when mshr_type==Texture Fifo
-# Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP100 has 64KB Shared memory
--gpgpu_cache:dl1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:64:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_shmem_size 65536
--gpgpu_shmem_size_PrefL1 65536
--gpgpu_shmem_size_PrefShared 65536
--gmem_skip_L1D 0
--icnt_flit_size 40
--gpgpu_n_cluster_ejection_buffer_size 32
-
-# 32 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives  4MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:4,32:0,32
--gpgpu_cache:dl2_texture_only 0 
--gpgpu_dram_partition_queues 64:64:64:64
--perf_sim_memcpy 0
--memory_partition_indexing 2
-
-# 4 KB Inst.
--gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
-# 48 KB Tex 
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
-# 12 KB Const
--gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
-
-# enable operand collector 
--gpgpu_operand_collector_num_units_sp 12
--gpgpu_operand_collector_num_units_sfu 6
--gpgpu_operand_collector_num_units_mem 8
--gpgpu_operand_collector_num_units_dp 6
--gpgpu_operand_collector_num_in_ports_sp 4
--gpgpu_operand_collector_num_out_ports_sp 4
--gpgpu_operand_collector_num_in_ports_sfu 1
--gpgpu_operand_collector_num_out_ports_sfu 1
--gpgpu_operand_collector_num_in_ports_mem 1
--gpgpu_operand_collector_num_out_ports_mem 1
--gpgpu_operand_collector_num_in_ports_dp 1
--gpgpu_operand_collector_num_out_ports_dp 1
--gpgpu_num_reg_banks 32
-
-# shared memory bankconflict detection 
--gpgpu_shmem_num_banks 32
--gpgpu_shmem_limited_broadcast 0
--gpgpu_shmem_warp_parts 1
--gpgpu_coalesce_arch 60
-
-## In Pascal, a warp scheduler can issue 2 insts per cycle using 2 diff execution units
--gpgpu_max_insn_issue_per_warp 2
--gpgpu_dual_issue_diff_exec_units 1
-
-# interconnection
--network_mode 1 
--inter_config_file config_fermi_islip.icnt
-
-# memory partition latency config 
--rop_latency 120
--dram_latency 100
-
-# dram model config
--gpgpu_dram_scheduler 1
-# The DRAM return queue and the scheduler queue together should provide buffer
-# to sustain the memory level parallelism to tolerate DRAM latency 
-# To allow 100% DRAM utility, there should at least be enough buffer to sustain
-# the minimum DRAM latency (100 core cycles).  I.e. 
-#   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 64
--gpgpu_dram_return_queue_size 192
-
-# for HBM, 32 channles, each (128 bits) 16 bytes width
--gpgpu_n_mem_per_ctrlr 1
--gpgpu_dram_buswidth 16
--gpgpu_dram_burst_length 2
--dram_data_command_freq_ratio 2  # HBM is DDR
--gpgpu_mem_address_mask 1
--gpgpu_mem_addr_mapping dramid@8;00000000.00000000.00000000.00000000.0000RRRR.RRRRRRRR.RBBBBCCC.CCCSSSSS
-
-# HBM timing are adopted from hynix JESD235 standered and nVidia HPCA 2017 paper (http://www.cs.utah.edu/~nil/pubs/hpca17.pdf)
-# Timing for 1 GHZ
-# tRRDl and tWTR are missing, need to be added
-#-gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=4:RCD=14:RAS=33:RP=14:RC=47:
-#                        CL=14:WL=2:CDLR=3:WR=12:nbkgrp=4:CCDL=2:RTPL=4"
-
-# Timing for 715 MHZ, Tesla Pascal P100 HBM runs at 715 MHZ
--gpgpu_dram_timing_opt "nbk=16:CCD=1:RRD=3:RCD=10:RAS=24:RP=10:RC=34:
-                        CL=10:WL=2:CDLR=3:WR=9:nbkgrp=4:CCDL=2:RTPL=3"
-
-# HBM has dual bus interface, in which it can issue two col and row commands at a time
--dual_bus_interface 1
-# select lower bits for bnkgrp to increase bnkgrp parallelism
--dram_bnk_indexing_policy 0
--dram_bnkgrp_indexing_policy 1
-
-#-Seperate_Write_Queue_Enable 1
-#-Write_Queue_Size 64:56:32
-
-# Pascal has two schedulers per core
--gpgpu_num_sched_per_core 2
-# Two Level Scheduler with active and pending pools
-#-gpgpu_scheduler two_level_active:6:0:1
-# Loose round robbin scheduler
-#-gpgpu_scheduler lrr
-# Greedy then oldest scheduler
--gpgpu_scheduler gto
-
-# stat collection
--gpgpu_memlatency_stat 14 
--gpgpu_runtime_stat 500
--enable_ptx_file_line_stats 1
--visualizer_enabled 0
-
-# power model configs, disable it untill we create a real energy model for Pascal 100
--power_simulation_enabled 0
--gpuwattch_xml_file gpuwattch_gtx480.xml
-
-# tracing functionality
-#-trace_enabled 1
-#-trace_components WARP_SCHEDULER,SCOREBOARD
-#-trace_sampling_core 0
-
diff --git a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
index 7368882..9ea7202 100644
--- a/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
+++ b/configs/4.x-cfgs/SM6_TITANX/gpgpusim.config
@@ -56,24 +56,29 @@
 -ptx_opcode_initiation_sfu 4
 -ptx_opcode_latency_sfu 8
 
+
+# latencies and cache configs are adopted from:
+# https://arxiv.org/pdf/1804.06826.pdf
 # <nsets>:<bsize>:<assoc>,<rep>:<wr>:<alloc>:<wr_alloc>:<set_index_fn>,<mshr>:<N>:<merge>,<mq>:**<fifo_entry>
 # ** Optional parameter - Required when mshr_type==Texture Fifo
 # Note: Hashing set index function (H) only applies to a set size of 32 or 64. 
-# Pascal GP102 has 96KB Shared memory
-# Pascal GP102 has 24KB L1 cache
-# The defulat is to disable the L1 cache, unless cache modifieres is used
--gpgpu_cache:dl1  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefL1  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
--gpgpu_cache:dl1PrefShared  S:32:128:6,L:L:f:N:H,A:256:8,16:0,32
+# Pascal GP102 has 96KB Shared memory divided over 2 cores, each has 48KB
+# Pascal GP102 has 2 banks L1 cache, where each is 24KB L1 cache
+# The defulat is to disable the L1 cache, unless cache modifieres are used
+-gpgpu_cache:dl1  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefL1  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
+-gpgpu_cache:dl1PrefShared  S:48:128:4,L:L:s:N:H,A:256:8,16:0,32
 -gpgpu_shmem_size 49152
 -gpgpu_shmem_size_PrefL1 49152
 -gpgpu_shmem_size_PrefShared 49152
 -gmem_skip_L1D 1
 -icnt_flit_size 40
 -gpgpu_n_cluster_ejection_buffer_size 32
+-l1_latency 82
+-smem_latency 24
 
 # 64 sets, each 128 bytes 16-way for each memory sub partition (128 KB per memory sub partition). This gives 3MB L2 cache
--gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:128:4,16:0,32
+-gpgpu_cache:dl2 S:64:128:16,L:B:m:L:L,A:256:64,16:0,32
 -gpgpu_cache:dl2_texture_only 0 
 -gpgpu_dram_partition_queues 32:32:32:32
 -perf_sim_memcpy 0
@@ -81,8 +86,7 @@
 # 4 KB Inst.
 -gpgpu_cache:il1 N:8:128:4,L:R:f:N:L,S:2:48,4
 # 48 KB Tex 
-# this is unused
--gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,F:128:4,128:2
+-gpgpu_tex_cache:l1 N:16:128:24,L:R:m:N:L,T:128:4,128:2
 # 12 KB Const
 -gpgpu_const_cache:l1 N:128:64:2,L:R:f:N:L,S:2:64,4
 
@@ -99,7 +103,6 @@
 -gpgpu_operand_collector_num_out_ports_mem 1
 -gpgpu_operand_collector_num_in_ports_dp 1
 -gpgpu_operand_collector_num_out_ports_dp 1
-# gpgpu_num_reg_banks should be increased to 32
 -gpgpu_num_reg_banks 32
 
 # shared memory bankconflict detection 
@@ -118,7 +121,7 @@
 -inter_config_file config_fermi_islip.icnt
 
 # memory partition latency config 
--rop_latency 100
+-rop_latency 120
 -dram_latency 100
 
 # dram model config
@@ -128,7 +131,7 @@
 # To allow 100% DRAM utility, there should at least be enough buffer to sustain
 # the minimum DRAM latency (100 core cycles).  I.e. 
 #   Total buffer space required = 100 x 924MHz / 700MHz = 132
--gpgpu_frfcfs_dram_sched_queue_size 16
+-gpgpu_frfcfs_dram_sched_queue_size 64
 -gpgpu_dram_return_queue_size 240
 
 # for NVIDIA TITAN X, bus width is 384bits (12 DRAM chips x 32 bits)