0.9756 correlation. Set L1T line size to 128 bytes... problem was

stalling to send four requests per warp into L1T tag lookup.

If L1T is really 32B blocks (as per Henry's paper), this suggests 
banking of L1T needs to be modeled. 

Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]

1 files changed, 22 insertions, 19 deletions

diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index 7acd9bb..3f2883a 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -108,7 +108,7 @@ void warp_inst_t::generate_mem_accesses()
     }
 
     // Calculate memory accesses generated by this warp
-    new_addr_type cache_block_size = 32; // in bytes 
+    new_addr_type cache_block_size = 0; // in bytes 
 
     switch( space.get_type() ) {
     case shared_space: {
@@ -186,25 +186,9 @@ void warp_inst_t::generate_mem_accesses()
 
     case tex_space: 
         cache_block_size = m_config->gpgpu_cache_texl1_linesize;
-
+        break;
     case const_space:  case param_space_kernel:
-        cache_block_size = m_config->gpgpu_cache_constl1_linesize; {
-        mem_access_byte_mask_t byte_mask; 
-        std::map<new_addr_type,active_mask_t> accesses; // block address -> set of thread offsets in warp
-        std::map<new_addr_type,active_mask_t>::iterator a;
-        for( unsigned thread=0; thread < m_config->warp_size; thread++ ) {
-            if( !active(thread) ) 
-                continue;
-            new_addr_type addr = m_per_scalar_thread[thread].memreqaddr;
-            unsigned block_address = line_size_based_tag_func(addr,m_config->gpgpu_cache_texl1_linesize);
-            accesses[block_address].set(thread);
-            unsigned idx = addr-block_address; 
-            for( unsigned i=0; i < data_size; i++ ) 
-                byte_mask.set(idx+i);
-        }
-        for( a=accesses.begin(); a != accesses.end(); ++a ) 
-            m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) );
-        }
+        cache_block_size = m_config->gpgpu_cache_constl1_linesize; 
         break;
 
     case global_space: case local_space: case param_space_local:
@@ -301,5 +285,24 @@ void warp_inst_t::generate_mem_accesses()
         abort();
     }
 
+    if( cache_block_size ) {
+        assert( m_accessq.empty() );
+        mem_access_byte_mask_t byte_mask; 
+        std::map<new_addr_type,active_mask_t> accesses; // block address -> set of thread offsets in warp
+        std::map<new_addr_type,active_mask_t>::iterator a;
+        for( unsigned thread=0; thread < m_config->warp_size; thread++ ) {
+            if( !active(thread) ) 
+                continue;
+            new_addr_type addr = m_per_scalar_thread[thread].memreqaddr;
+            unsigned block_address = line_size_based_tag_func(addr,cache_block_size);
+            accesses[block_address].set(thread);
+            unsigned idx = addr-block_address; 
+            for( unsigned i=0; i < data_size; i++ ) 
+                byte_mask.set(idx+i);
+        }
+        for( a=accesses.begin(); a != accesses.end(); ++a ) 
+            m_accessq.push_back( mem_access_t(access_type,a->first,cache_block_size,is_write,a->second,byte_mask) );
+    }
+
     m_mem_accesses_created=true;
 }