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authorTor Aamodt <[email protected]>2010-10-09 07:58:44 -0800
committerTor Aamodt <[email protected]>2010-10-09 07:58:44 -0800
commit4fce546cc9778b889bd07cf852be29b70a44f47d (patch)
tree212ac4a08cd777ef329cbaa7f74da730c82be1df /src/abstract_hardware_model.cc
parentb64d38562079a7d4720c15c9f6309912f4090795 (diff)
Refactoring:
1. Moving mem_access_t to abstract_hardware_model and making set (queue) of accesses part of warp_inst_t. I.e., treat set of accesses as an ISA concept rather than a hardware organization concept. This is only partly "done"... logic for computing accesses is still part of shader_core_ctx in this CL. Given number of warp_inst_t accessors for accessq, now seems like we might even want to move some memory stage code into warp_inst_t class. How those accesses make it to memory system is the hardware concept. 2. Making warp_inst_t an explicit arguement of subroutines used in memory stage... The eventual goal here is (likely) to refactor memory into a hardware block... i.e., have function units be a class that contains some set of pipeline stages internally and some set of input/output "ports". 3. Moving accessor functions is_load, is_store; is_const, is_local into class declaration (where they belong). 4. Removing code for selecting pipeline uarch (might add it back later, but first want a clean GT200 organization). In particular, removing option to have an operand collector -- now you MUST have the operand collector. 5. Removing more deadcode from prior changes (fixed delay queue related) Scripts/configs: 6. Correlation script not printing out exit condition when hardware launch fails 7. Update config files to have proper compute model selected [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7834]
Diffstat (limited to 'src/abstract_hardware_model.cc')
-rw-r--r--src/abstract_hardware_model.cc8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/abstract_hardware_model.cc b/src/abstract_hardware_model.cc
index a0e21f7..c52be1d 100644
--- a/src/abstract_hardware_model.cc
+++ b/src/abstract_hardware_model.cc
@@ -1,5 +1,8 @@
#include "abstract_hardware_model.h"
#include "cuda-sim/memory.h"
+#include <algorithm>
+
+unsigned mem_access_t::next_access_uid = 0;
void move_warp( warp_inst_t *&dst, warp_inst_t *&src )
{
@@ -19,3 +22,8 @@ gpgpu_t::gpgpu_t()
g_dev_malloc=GLOBAL_HEAP_START;
}
+
+void warp_inst_t::sort_accessq( unsigned qbegin )
+{
+ std::stable_sort( m_accessq.begin()+qbegin,m_accessq.end());
+}