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authorDavit Grigoryan <[email protected]>2026-05-01 10:29:50 +0000
committerDavit Grigoryan <[email protected]>2026-05-01 10:29:50 +0000
commit2e35f844aac74403fc3021682fab0231195a69d3 (patch)
tree4fa0e341a20565a20e53e29ef2c6496d931ace46 /src/abstract_hardware_model.h
parent8ccb5a12c97bfbe04b783b779e518ac7cf08d91a (diff)
fix double sb from fifo rotations during intra coissue
Diffstat (limited to 'src/abstract_hardware_model.h')
-rw-r--r--src/abstract_hardware_model.h11
1 files changed, 11 insertions, 0 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h
index 09d59f9..8d1e0e8 100644
--- a/src/abstract_hardware_model.h
+++ b/src/abstract_hardware_model.h
@@ -1934,6 +1934,16 @@ class simt_tables {
return m_simt_splits_table->move_split_to_front(split_id);
}
+ // Mode 2 (slot-pinned scoreboard) cross-slot drain gate. Set by
+ // simt_tables::update() when the FIFO membership changes due to actual
+ // divergence (num_divergent_paths > 1) or reconvergence (active mask
+ // grows on RPC merge). NOT set by co-issue's move_split_to_front
+ // (FIFO ordering change without membership change). Cleared by the
+ // fetch-stage gate once both slot scoreboards are observed clean.
+ bool div_recv_drain_pending() const { return m_div_recv_drain_pending; }
+ void set_div_recv_drain_pending() { m_div_recv_drain_pending = true; }
+ void clear_div_recv_drain_pending() { m_div_recv_drain_pending = false; }
+
private:
unsigned m_warp_id;
unsigned m_warp_size;
@@ -1942,6 +1952,7 @@ class simt_tables {
const shader_core_config *m_config;
const struct memory_config *m_mem_config;
shader_core_ctx *m_shader;
+ bool m_div_recv_drain_pending = false;
};
// ── End ITS data structures ─────────────────────────────────────────────────