diff options
| author | Davit Grigoryan <[email protected]> | 2026-04-08 07:14:50 +0000 |
|---|---|---|
| committer | Davit Grigoryan <[email protected]> | 2026-04-08 07:14:50 +0000 |
| commit | 6fe5349343b27a8919734fb4900dd2324cdf6c60 (patch) | |
| tree | cdb60316dd273893375f876a367f9e17a7604f82 /src/abstract_hardware_model.h | |
| parent | 56550cce3389357bf0bb2c1fdc7d9a6edbc319ab (diff) | |
add simple simd lane set partitioning
Diffstat (limited to 'src/abstract_hardware_model.h')
| -rw-r--r-- | src/abstract_hardware_model.h | 34 |
1 files changed, 33 insertions, 1 deletions
diff --git a/src/abstract_hardware_model.h b/src/abstract_hardware_model.h index e96ddc4..948e226 100644 --- a/src/abstract_hardware_model.h +++ b/src/abstract_hardware_model.h @@ -1109,6 +1109,24 @@ enum divergence_support_t { const unsigned MAX_ACCESSES_PER_INSN_PER_THREAD = 8; +// SIMD lane partitioning: per-set execution data +struct simd_set_info { + unsigned set_id; // Set index (0 to num_sets-1) + unsigned warp_id; // Owning warp + simt_mask_t set_active_mask; // Active lanes within this set (lower set_width bits) + active_mask_t active_mask_in_warp; // Active mask in original 32-bit warp thread domain + unsigned thread_ids[MAX_WARP_SIZE]; // Original thread IDs for each lane (max set_width used) + unsigned num_active_threads; // popcount of set_active_mask + bool valid; // Whether this set has any active threads + + simd_set_info() + : set_id(0), warp_id(0), num_active_threads(0), valid(false) { + set_active_mask.reset(); + active_mask_in_warp.reset(); + for (unsigned i = 0; i < MAX_WARP_SIZE; i++) thread_ids[i] = 0; + } +}; + class warp_inst_t : public inst_t { public: // constructors @@ -1152,12 +1170,23 @@ class warp_inst_t : public inst_t { void broadcast_barrier_reduction(const active_mask_t &access_mask); void do_atomic(bool forceDo = false); void do_atomic(const active_mask_t &access_mask, bool forceDo = false); - void clear() { m_empty = true; } + void clear() { + m_empty = true; + m_simd_sets.clear(); + } void issue(const active_mask_t &mask, unsigned warp_id, unsigned long long cycle, int dynamic_warp_id, int sch_id, unsigned long long streamID); + // SIMD lane partitioning + void compute_simd_sets(unsigned num_sets, unsigned set_width); + const std::vector<simd_set_info> &get_simd_sets() const { + return m_simd_sets; + } + unsigned num_active_simd_sets() const; + bool has_simd_sets() const { return !m_simd_sets.empty(); } + const active_mask_t &get_active_mask() const { return m_warp_active_mask; } void completed(unsigned long long cycle) const; // stat collection: called when the instruction is completed @@ -1333,6 +1362,9 @@ class warp_inst_t : public inst_t { unsigned m_scheduler_id; // the scheduler that issues this inst + // SIMD lane partitioning data + std::vector<simd_set_info> m_simd_sets; + // Jin: cdp support public: int m_is_cdp; |
