diff options
| author | Tor Aamodt <[email protected]> | 2010-10-24 23:41:43 -0800 |
|---|---|---|
| committer | Tor Aamodt <[email protected]> | 2010-10-24 23:41:43 -0800 |
| commit | 0efd3c00f5611bfa82b01d87d175122388d621cc (patch) | |
| tree | b86c29b46a2bdf1586dd1d321e760c71df841d3f /src/cuda-sim/cuda-sim.cc | |
| parent | 826a0dc10ca939af1f2c24d0d2e63eb2b33cb731 (diff) | |
0.9756 correlation. Set L1T line size to 128 bytes... problem was
stalling to send four requests per warp into L1T tag lookup.
If L1T is really 32B blocks (as per Henry's paper), this suggests
banking of L1T needs to be modeled.
Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]
Diffstat (limited to 'src/cuda-sim/cuda-sim.cc')
| -rw-r--r-- | src/cuda-sim/cuda-sim.cc | 20 |
1 files changed, 5 insertions, 15 deletions
diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc index 1982218..b1893a0 100644 --- a/src/cuda-sim/cuda-sim.cc +++ b/src/cuda-sim/cuda-sim.cc @@ -142,21 +142,11 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te printf("GPGPU-Sim PTX: texture cache linesize = %d\n", m_function_model_config.get_texcache_linesize()); //first determine base Tx size for given linesize switch (m_function_model_config.get_texcache_linesize()) { - case 16: - Tx = 4; - break; - case 32: - Tx = 8; - break; - case 64: - Tx = 8; - break; - case 128: - Tx = 16; - break; - case 256: - Tx = 16; - break; + case 16: Tx = 4; break; + case 32: Tx = 8; break; + case 64: Tx = 8; break; + case 128: Tx = 16; break; + case 256: Tx = 16; break; default: printf("GPGPU-Sim PTX: Line size of %d bytes currently not supported.\n", m_function_model_config.get_texcache_linesize()); assert(0); |