Merging Power model into Fermi

//depot/gpgpu_sim_research/fermi_power/distribution/...

to //depot/gpgpu_sim_research/fermi/distribution/...

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]

1 files changed, 88 insertions, 1 deletions

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index 8e01fe7..368ac4a 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -451,7 +451,81 @@ void ptx_print_insn( address_type pc, FILE *fp )
    assert( finfo );
    size = finfo->print_insn(pc,fp);
 }
+void ptx_instruction::set_fp_or_int_archop(){
+	op2=UN_OP;
+	if((m_opcode == SSY_OP )||(m_opcode == BRA_OP) || (m_opcode == BAR_OP) || (m_opcode == RET_OP) || (m_opcode == RETP_OP) || (m_opcode == NOP_OP) || (m_opcode == EXIT_OP) || (m_opcode == CALLP_OP) || (m_opcode == CALL_OP)){
+			// do nothing
+	}else if((m_opcode == CVT_OP || m_opcode == SET_OP || m_opcode == SLCT_OP)){
+		if(get_type2()==F16_TYPE || get_type2()==F32_TYPE || get_type2() == F64_TYPE || get_type2() == FF64_TYPE){
+			op2= FP_OP;
+		}else op2=INT_OP;
 
+	}else{
+		if(get_type()==F16_TYPE || get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){
+			op2= FP_OP;
+		}else op2=INT_OP;
+	}
+}
+void ptx_instruction::set_mul_div_or_other_archop(){
+	op3=OTHER_OP;
+	if((m_opcode != SSY_OP) && (m_opcode != BRA_OP) && (m_opcode != BAR_OP) && (m_opcode != EXIT_OP) && (m_opcode != NOP_OP) && (m_opcode != RETP_OP) && (m_opcode != RET_OP) && (m_opcode != CALLP_OP) && (m_opcode != CALL_OP)){
+		if(get_type()==F32_TYPE || get_type() == F64_TYPE || get_type() == FF64_TYPE){
+			switch(get_opcode()){
+				case MUL_OP:
+				case MAD_OP:
+					op3=FP_MUL_OP;
+					break;
+				case DIV_OP:
+					op3=FP_DIV_OP;
+					break;
+				case LG2_OP:
+					op3=FP_LG_OP;
+					break;
+				case RSQRT_OP:
+				case SQRT_OP:
+					op3=FP_SQRT_OP;
+					break;
+				case RCP_OP:
+               op3=FP_DIV_OP;
+					break;
+				case SIN_OP:
+				case COS_OP:
+					op3=FP_SIN_OP;
+					break;
+				case EX2_OP:
+					op3=FP_EXP_OP;
+					break;
+				default:
+					if(op==ALU_OP)
+						op3=FP__OP;
+					break;
+
+			}
+		}else {
+			switch(get_opcode()){
+				case MUL24_OP:
+				case MAD24_OP:
+					op3=INT_MUL24_OP;
+				break;
+				case MUL_OP:
+				case MAD_OP:
+					if(get_type()==U32_TYPE || get_type()==S32_TYPE || get_type()==B32_TYPE)
+						op3=INT_MUL32_OP;
+					else
+						op3=INT_MUL_OP;
+				break;
+				case DIV_OP:
+					op3=INT_DIV_OP;
+				break;
+				default:
+					if(op==ALU_OP)
+						op3=INT__OP;
+					break;
+			}
+		}
+	}
+
+}
 void ptx_instruction::set_opcode_and_latency()
 {
 	unsigned int_latency[5];
@@ -486,7 +560,17 @@ void ptx_instruction::set_opcode_and_latency()
 			&dp_init[0],&dp_init[1],&dp_init[2],
 			&dp_init[3],&dp_init[4]);
 
+	if(!m_operands.empty()){
+		std::vector<operand_info>::iterator it;
+	   	for(it=++m_operands.begin();it!=m_operands.end();it++){
+	   		num_operands++;
+	   		if((it->is_reg() || it->is_vector())){
+	   			   num_regs++;
+	   		}
+	   	 }
+	}
    op = ALU_OP;
+   op5= NOT_TEX;
    initiation_interval = latency = 1;
    switch( m_opcode ) {
    case MOV_OP:
@@ -499,7 +583,7 @@ void ptx_instruction::set_opcode_and_latency()
    case ST_OP: op = STORE_OP; break;
    case BRA_OP: op = BRANCH_OP; break;
    case BREAKADDR_OP: op = BRANCH_OP; break;
-   case TEX_OP: op = LOAD_OP; break;
+   case TEX_OP: op = LOAD_OP; op5=TEX; break;
    case ATOM_OP: op = LOAD_OP; break;
    case BAR_OP: op = BARRIER_OP; break;
    case MEMBAR_OP: op = MEMORY_BARRIER_OP; break;
@@ -639,6 +723,9 @@ void ptx_instruction::set_opcode_and_latency()
    default: 
        break;
    }
+	set_fp_or_int_archop();
+	set_mul_div_or_other_archop();
+
 }
 
 void ptx_thread_info::ptx_fetch_inst( inst_t &inst ) const