0.9756 correlation. Set L1T line size to 128 bytes... problem was

stalling to send four requests per warp into L1T tag lookup.

If L1T is really 32B blocks (as per Henry's paper), this suggests 
banking of L1T needs to be modeled. 

Other changes:
1. bug fix in memory access generation for texture/const cache access
2. adding back memory latency measurement for visualizer

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7913]

1 files changed, 2 insertions, 5 deletions

diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 2b6ce9c..ad2eb43 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -3745,11 +3745,8 @@ void tex_impl( const ptx_instruction *pI, ptx_thread_info *thread )
       thread->m_last_effective_address = tex_array_index;
       break;
    case GEOM_MODIFIER_2D: 
-      x_block_coord = x;
-      x_block_coord = x_block_coord >> (texInfo->Tx_numbits + texInfo->texel_size_numbits);
-
-      y_block_coord = y;
-      y_block_coord = y_block_coord >> texInfo->Ty_numbits;
+      x_block_coord = x >> (texInfo->Tx_numbits + texInfo->texel_size_numbits);
+      y_block_coord = y >> texInfo->Ty_numbits;
 
       memreqindex = ((y_block_coord*cuArray->width/texInfo->Tx)+x_block_coord)<<6;