Adding support in the simulator for addition with carry specified in a given predicate register (calling it addp)

Adding support in cuobjdump_to_ptxplus for IADD.CARRY* which translates to the above
Now power benchmarks should work

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 12266]

1 files changed, 71 insertions, 0 deletions

diff --git a/src/cuda-sim/instructions.cc b/src/cuda-sim/instructions.cc
index 4537bd0..fd9a9ac 100644
--- a/src/cuda-sim/instructions.cc
+++ b/src/cuda-sim/instructions.cc
@@ -674,6 +674,77 @@ void abs_impl( const ptx_instruction *pI, ptx_thread_info *thread )
    thread->set_operand_value(dst,d, i_type, thread, pI);
 }
 
+void addp_impl( const ptx_instruction *pI, ptx_thread_info *thread )
+{
+   //PTXPlus add instruction with carry (carry is kept in a predicate) register
+   ptx_reg_t src1_data, src2_data, src3_data, data;
+   int overflow = 0;
+   int carry = 0;
+
+   const operand_info &dst  = pI->dst();  //get operand info of sources and destination
+   const operand_info &src1 = pI->src1(); //use them to determine that they are of type 'register'
+   const operand_info &src2 = pI->src2();
+   const operand_info &src3 = pI->src3();
+
+   unsigned i_type = pI->get_type();
+   src1_data = thread->get_operand_value(src1, dst, i_type, thread, 1);
+   src2_data = thread->get_operand_value(src2, dst, i_type, thread, 1);
+   src3_data = thread->get_operand_value(src3, dst, i_type, thread, 1);
+
+   unsigned rounding_mode = pI->rounding_mode();
+   int orig_rm = fegetround();
+   switch ( rounding_mode ) {
+   case RN_OPTION: break;
+   case RZ_OPTION: fesetround( FE_TOWARDZERO ); break;
+   default: assert(0); break;
+   }
+
+   //performs addition. Sets carry and overflow if needed.
+   //src3_data.pred&0x4 is the carry flag
+   switch ( i_type ) {
+   case S8_TYPE:
+      data.s64 = (src1_data.s64 & 0x0000000FF) + (src2_data.s64 & 0x0000000FF) + (src3_data.pred & 0x4);
+      if(((src1_data.s64 & 0x80)-(src2_data.s64 & 0x80)) == 0) {overflow=((src1_data.s64 & 0x80)-(data.s64 & 0x80))==0?0:1; }
+      carry = (data.u64 & 0x000000100)>>8;
+      break;
+   case S16_TYPE:
+      data.s64 = (src1_data.s64 & 0x00000FFFF) + (src2_data.s64 & 0x00000FFFF) + (src3_data.pred & 0x4);
+      if(((src1_data.s64 & 0x8000)-(src2_data.s64 & 0x8000)) == 0) {overflow=((src1_data.s64 & 0x8000)-(data.s64 & 0x8000))==0?0:1; }
+      carry = (data.u64 & 0x000010000)>>16;
+      break;
+   case S32_TYPE:
+      data.s64 = (src1_data.s64 & 0x0FFFFFFFF) + (src2_data.s64 & 0x0FFFFFFFF) + (src3_data.pred & 0x4);
+      if(((src1_data.s64 & 0x80000000)-(src2_data.s64 & 0x80000000)) == 0) {overflow=((src1_data.s64 & 0x80000000)-(data.s64 & 0x80000000))==0?0:1; }
+      carry = (data.u64 & 0x100000000)>>32;
+      break;
+   case S64_TYPE:
+      data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4);
+      break;
+   case U8_TYPE:
+      data.u64 = (src1_data.u64 & 0xFF) + (src2_data.u64 & 0xFF) + (src3_data.pred & 0x4);
+      carry = (data.u64 & 0x100)>>8;
+      break;
+   case U16_TYPE:
+      data.u64 = (src1_data.u64 & 0xFFFF) + (src2_data.u64 & 0xFFFF) + (src3_data.pred & 0x4);
+      carry = (data.u64 & 0x10000)>>16;
+      break;
+   case U32_TYPE:
+      data.u64 = (src1_data.u64 & 0xFFFFFFFF) + (src2_data.u64 & 0xFFFFFFFF) + (src3_data.pred & 0x4);
+      carry = (data.u64 & 0x100000000)>>32;
+      break;
+   case U64_TYPE:
+      data.s64 = src1_data.s64 + src2_data.s64 + (src3_data.pred & 0x4);
+      break;
+   case F16_TYPE: assert(0); break;
+   case F32_TYPE: data.f32 = src1_data.f32 + src2_data.f32; break;
+   case F64_TYPE: case FF64_TYPE: data.f64 = src1_data.f64 + src2_data.f64; break;
+   default: assert(0); break;
+   }
+   fesetround( orig_rm );
+
+   thread->set_operand_value(dst, data, i_type, thread, pI, overflow, carry  );
+}
+
 void add_impl( const ptx_instruction *pI, ptx_thread_info *thread ) 
 { 
    ptx_reg_t src1_data, src2_data, data;