Add src/cuda-sim formatting

1 files changed, 39 insertions, 38 deletions

diff --git a/src/cuda-sim/opcodes.h b/src/cuda-sim/opcodes.h
index 86d3b99..479b1ca 100644
--- a/src/cuda-sim/opcodes.h
+++ b/src/cuda-sim/opcodes.h
@@ -7,14 +7,16 @@
 //
 // Redistributions of source code must retain the above copyright notice, this
 // list of conditions and the following disclaimer.
-// Redistributions in binary form must reproduce the above copyright notice, this
+// Redistributions in binary form must reproduce the above copyright notice,
+// this
 // list of conditions and the following disclaimer in the documentation and/or
 // other materials provided with the distribution.
 // Neither the name of The University of British Columbia nor the names of its
 // contributors may be used to endorse or promote products derived from this
 // software without specific prior written permission.
 //
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND
 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
@@ -29,49 +31,48 @@
 #define opcodes_h_included
 
 enum opcode_t {
-#define OP_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP,
-#define OP_W_DEF(OP,FUNC,STR,DST,CLASSIFICATION) OP,
+#define OP_DEF(OP, FUNC, STR, DST, CLASSIFICATION) OP,
+#define OP_W_DEF(OP, FUNC, STR, DST, CLASSIFICATION) OP,
 #include "opcodes.def"
-	NUM_OPCODES
+  NUM_OPCODES
 #undef OP_DEF
 #undef OP_W_DEF
 };
 
 enum special_regs {
-   CLOCK_REG,
-   HALFCLOCK_ID,
-   CLOCK64_REG,
-   CTAID_REG,
-   ENVREG_REG,
-   GRIDID_REG,
-   LANEID_REG,
-   LANEMASK_EQ_REG,
-   LANEMASK_LE_REG,
-   LANEMASK_LT_REG,
-   LANEMASK_GE_REG,
-   LANEMASK_GT_REG,
-   NCTAID_REG,
-   NTID_REG,
-   NSMID_REG,
-   NWARPID_REG,
-   PM_REG,
-   SMID_REG,
-   TID_REG,
-   WARPID_REG,
-   WARPSZ_REG
+  CLOCK_REG,
+  HALFCLOCK_ID,
+  CLOCK64_REG,
+  CTAID_REG,
+  ENVREG_REG,
+  GRIDID_REG,
+  LANEID_REG,
+  LANEMASK_EQ_REG,
+  LANEMASK_LE_REG,
+  LANEMASK_LT_REG,
+  LANEMASK_GE_REG,
+  LANEMASK_GT_REG,
+  NCTAID_REG,
+  NTID_REG,
+  NSMID_REG,
+  NWARPID_REG,
+  PM_REG,
+  SMID_REG,
+  TID_REG,
+  WARPID_REG,
+  WARPSZ_REG
 };
-enum wmma_type{
-	LOAD_A,
-	LOAD_B,
-	LOAD_C,
-	STORE_D,
-	MMA,
-	ROW,
-	COL,
-	M16N16K16,
-	M32N8K16,
-	M8N32K16
-
+enum wmma_type {
+  LOAD_A,
+  LOAD_B,
+  LOAD_C,
+  STORE_D,
+  MMA,
+  ROW,
+  COL,
+  M16N16K16,
+  M32N8K16,
+  M8N32K16
 
 };
 #endif