1. adding top level configuration class and making shader and memory configuration

   components of this class.
2. clock memory pipeline no. subwarp times for each shader clock and increase
   rob-size for texture cache (trying to improve correlation, currently at 0.9218)
3. start to modify shader stats to add back features for visualizer (warp 
   divergence distribution kind of working again)

passing cuda 3.1 regression and ptxplus correlation tests

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7909]

5 files changed, 22 insertions, 26 deletions

diff --git a/src/cuda-sim/cuda-sim.cc b/src/cuda-sim/cuda-sim.cc
index d429dc3..1967b2f 100644
--- a/src/cuda-sim/cuda-sim.cc
+++ b/src/cuda-sim/cuda-sim.cc
@@ -92,7 +92,6 @@ int g_debug_execution = 0;
 int g_debug_thread_uid = 0;
 addr_t g_debug_pc = 0xBEEF1518;
 // Output debug information to file options
-FILE* ptx_inst_debug_file;
 
 unsigned g_ptx_sim_num_insn = 0;
 unsigned gpgpu_param_num_shaders = 0;
@@ -140,9 +139,9 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te
    int r;
 
    printf("GPGPU-Sim PTX:   texel size = %d\n", texel_size);
-   printf("GPGPU-Sim PTX:   texture cache linesize = %d\n", m_texcache_linesize);
+   printf("GPGPU-Sim PTX:   texture cache linesize = %d\n", m_function_model_config.get_texcache_linesize());
    //first determine base Tx size for given linesize
-   switch (m_texcache_linesize) {
+   switch (m_function_model_config.get_texcache_linesize()) {
    case 16:
       Tx = 4;
       break;
@@ -159,7 +158,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te
       Tx = 16;
       break;
    default:
-      printf("GPGPU-Sim PTX:   Line size of %d bytes currently not supported.\n", m_texcache_linesize);
+      printf("GPGPU-Sim PTX:   Line size of %d bytes currently not supported.\n", m_function_model_config.get_texcache_linesize());
       assert(0);
       break;
    }
@@ -170,7 +169,7 @@ void gpgpu_t::gpgpu_ptx_sim_bindTextureToArray(const struct textureReference* te
       r = r >> 2;
    }
    //by now, got the correct Tx size, calculate correct Ty size
-   Ty = m_texcache_linesize/(Tx*texel_size);
+   Ty = m_function_model_config.get_texcache_linesize()/(Tx*texel_size);
 
    printf("GPGPU-Sim PTX:   Tx = %d; Ty = %d, Tx_numbits = %d, Ty_numbits = %d\n", Tx, Ty, intLOGB2(Tx), intLOGB2(Ty));
    printf("GPGPU-Sim PTX:   Texel size = %d bytes; texel_size_numbits = %d\n", texel_size, intLOGB2(texel_size));
@@ -850,7 +849,7 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id )
       printf("attempted to execute instruction on a thread that is already done.\n");
       assert(0);
    }
-   if ( g_debug_execution >= 6 || g_ptx_inst_debug_to_file) {
+   if ( g_debug_execution >= 6 || m_gpu->get_config().get_ptx_inst_debug_to_file()) {
       if ( (g_debug_thread_uid==0) || (get_uid() == (unsigned)g_debug_thread_uid) ) {
          clear_modifiedregs();
          enable_debug_trace();
@@ -889,17 +888,19 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id )
          exit_impl(pI,this);
    }
 
+   const gpgpu_functional_sim_config &config = m_gpu->get_config();
+   
    // Output instruction information to file and stdout
-   if( g_ptx_inst_debug_to_file != 0 && 
-        (g_ptx_inst_debug_thread_uid == 0 || g_ptx_inst_debug_thread_uid == get_uid()) ) {
+   if( config.get_ptx_inst_debug_to_file() != 0 && 
+        (config.get_ptx_inst_debug_thread_uid() == 0 || config.get_ptx_inst_debug_thread_uid() == get_uid()) ) {
       dim3 ctaid = get_ctaid();
       dim3 tid = get_tid();
-      fprintf(ptx_inst_debug_file,
+      fprintf(m_gpu->get_ptx_inst_debug_file(),
              "[thd=%u] : (%s:%u - %s)\n",
              get_uid(),
              pI->source_file(), pI->source_line(), pI->get_source() );
       //fprintf(ptx_inst_debug_file, "has memory read=%d, has memory write=%d\n", pI->has_memory_read(), pI->has_memory_write());
-      fflush(ptx_inst_debug_file);
+      fflush(m_gpu->get_ptx_inst_debug_file());
    }
 
    if ( ptx_debug_exec_dump_cond<5>(get_uid(), pc) ) {
@@ -965,10 +966,10 @@ void ptx_thread_info::ptx_exec_inst( warp_inst_t &inst, unsigned lane_id )
    }
 
    // Output register information to file and stdout
-   if( g_ptx_inst_debug_to_file != 0 && 
-        (g_ptx_inst_debug_thread_uid == 0 || g_ptx_inst_debug_thread_uid == get_uid()) ) {
-      dump_modifiedregs(ptx_inst_debug_file);
-      dump_regs(ptx_inst_debug_file);
+   if( config.get_ptx_inst_debug_to_file()!=0 && 
+       (config.get_ptx_inst_debug_thread_uid()==0||config.get_ptx_inst_debug_thread_uid()==get_uid()) ) {
+      dump_modifiedregs(m_gpu->get_ptx_inst_debug_file());
+      dump_regs(m_gpu->get_ptx_inst_debug_file());
    }
 
    if ( g_debug_execution >= 6 ) {
@@ -1031,7 +1032,7 @@ void set_param_gpgpu_num_shaders(int num_shaders)
    gpgpu_param_num_shaders = num_shaders;
 }
 
-const struct gpgpu_ptx_sim_kernel_info* ptx_sim_kernel_info(function_info *kernel) 
+const struct gpgpu_ptx_sim_kernel_info* ptx_sim_kernel_info(const function_info *kernel) 
 {
    return kernel->get_kernel_info();
 }
@@ -1468,12 +1469,6 @@ void gpgpu_cuda_ptx_sim_main_func( kernel_info_t kernel, dim3 gridDim, dim3 bloc
    fflush(stdout); 
 }
 
-unsigned gpgpu_t::ptx_set_tex_cache_linesize(unsigned linesize)
-{
-   m_texcache_linesize = linesize;
-   return 0;
-}
-
 unsigned translate_pc_to_ptxlineno(unsigned pc)
 {
    // this function assumes that the kernel fits inside a single PTX file
diff --git a/src/cuda-sim/cuda-sim.h b/src/cuda-sim/cuda-sim.h
index b095afb..0e97b97 100644
--- a/src/cuda-sim/cuda-sim.h
+++ b/src/cuda-sim/cuda-sim.h
@@ -18,7 +18,6 @@ extern int g_debug_thread_uid;
 extern void ** g_inst_classification_stat;
 extern void ** g_inst_op_classification_stat;
 extern int g_ptx_kernel_count; // used for classification stat collection purposes 
-extern FILE* ptx_inst_debug_file;
 
 
 extern class kernel_info_t gpgpu_opencl_ptx_sim_init_grid(class function_info *entry,
@@ -45,7 +44,7 @@ unsigned ptx_sim_init_thread( kernel_info_t &kernel,
                               unsigned hw_warp_id,
                               gpgpu_t *gpu );
 const warp_inst_t *ptx_fetch_inst( address_type pc );
-const struct gpgpu_ptx_sim_kernel_info* ptx_sim_kernel_info(class function_info *kernel);
+const struct gpgpu_ptx_sim_kernel_info* ptx_sim_kernel_info(const class function_info *kernel);
 void ptx_print_insn( address_type pc, FILE *fp );
 void set_param_gpgpu_num_shaders(int num_shaders);
 unsigned int get_converge_point(unsigned int pc, void *thd);
diff --git a/src/cuda-sim/ptx_ir.cc b/src/cuda-sim/ptx_ir.cc
index fee0056..50167b8 100644
--- a/src/cuda-sim/ptx_ir.cc
+++ b/src/cuda-sim/ptx_ir.cc
@@ -118,8 +118,8 @@ symbol_table::symbol_table( const char *scope_name, unsigned entry_point, symbol
 {
    m_scope_name = std::string(scope_name);
    m_reg_allocator=0;
-   m_shared_next = 0x100;
-   m_const_next  = 0x100;
+   m_shared_next = 0;
+   m_const_next  = 0;
    m_global_next = 0x100;
    m_local_next  = 0;
    m_parent = parent;
diff --git a/src/cuda-sim/ptx_ir.h b/src/cuda-sim/ptx_ir.h
index a8f9a7b..3d65712 100644
--- a/src/cuda-sim/ptx_ir.h
+++ b/src/cuda-sim/ptx_ir.h
@@ -1159,7 +1159,8 @@ public:
    void param_to_shared( memory_space *shared_mem, symbol_table *symtab ); 
    void list_param( FILE *fout ) const;
 
-   const struct gpgpu_ptx_sim_kernel_info* get_kernel_info () {
+   const struct gpgpu_ptx_sim_kernel_info* get_kernel_info () const
+   {
       return &m_kernel_info;
    }
 
diff --git a/src/cuda-sim/ptx_sim.h b/src/cuda-sim/ptx_sim.h
index 298122e..d60955b 100644
--- a/src/cuda-sim/ptx_sim.h
+++ b/src/cuda-sim/ptx_sim.h
@@ -430,6 +430,7 @@ public:
    memory_space *get_tex_memory() { return m_gpu->get_tex_memory(); }
    memory_space *get_surf_memory() { return m_gpu->get_surf_memory(); }
    memory_space *get_param_memory() { return m_gpu->get_param_memory(); }
+   const gpgpu_functional_sim_config &get_config() const { return m_gpu->get_config(); }
 
 public:
    addr_t         m_last_effective_address;