1. adding simt_core_cluster, which models a TPC or (for fermi) GPC...

   this gives us a place to stick caches shared among shader cores but
   on the shader side of the interconnect... maybe move the clock
   boundary code here? after integrating booksim 2 code?
2. added a pending write table to ldst_unit rather than scoreboard
   ... rationale is that ld/st unit needs to process register writes
   once it is done it can notify scoreboard once.
3. re-enabled shared memory delay (use pipeline within ldst_unit)
4. re-enabling operand collector writeback for all instruction types
5. disable MSHRs in this change list 

passing CUDA 3.1 regression

next? texture cache, then redo mshrs?

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 7845]

1 files changed, 2 insertions, 0 deletions

diff --git a/src/debug.cc b/src/debug.cc
index 236870c..49cae96 100644
--- a/src/debug.cc
+++ b/src/debug.cc
@@ -84,6 +84,7 @@ void gpgpu_sim::gpgpu_debug()
             done = false; 
          }
       } else {
+          /*
          for( unsigned sid=0; sid < m_n_shader; sid++ ) { 
             unsigned hw_thread_id = -1;
             abort();
@@ -101,6 +102,7 @@ void gpgpu_sim::gpgpu_debug()
                printf( "\n" );
             }
          }
+         */
       }
    }