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authorMahmoud <[email protected]>2019-08-26 12:17:52 -0400
committerMahmoud <[email protected]>2019-08-26 12:17:52 -0400
commitc2a1e3a668f9a88239184e13460f7e1725b15c90 (patch)
tree0546cc50d6e222072add55e36999a338b925d807 /src/gpgpu-sim/addrdec.cc
parent56c52cf6c4b369e9fd05759e9b16ea37ff6e332c (diff)
Banked L1, adding iSLIP and RR arbiteratio and adding some comments
Diffstat (limited to 'src/gpgpu-sim/addrdec.cc')
-rw-r--r--src/gpgpu-sim/addrdec.cc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/gpgpu-sim/addrdec.cc b/src/gpgpu-sim/addrdec.cc
index ca88ec9..b0db034 100644
--- a/src/gpgpu-sim/addrdec.cc
+++ b/src/gpgpu-sim/addrdec.cc
@@ -167,6 +167,8 @@ void linear_to_raw_address_translation::addrdec_tlx(new_addr_type addr, addrdec_
}
case RANDOM:
{
+ //This is an unrealistic hashing using software hashtable
+ //we generate a random set for each memory address and save the value in a big hashtable for future reuse
new_addr_type chip_address = (addr>>ADDR_CHIP_S);
tr1_hash_map<new_addr_type,unsigned>::const_iterator got = address_random_interleaving.find (chip_address);
if ( got == address_random_interleaving.end() ) {