Redesigned the memory partition unit to support multiple L2 cache banks per partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]

1 files changed, 5 insertions, 2 deletions

diff --git a/src/gpgpu-sim/addrdec.h b/src/gpgpu-sim/addrdec.h
index 94b113a..f16c9b1 100644
--- a/src/gpgpu-sim/addrdec.h
+++ b/src/gpgpu-sim/addrdec.h
@@ -43,13 +43,15 @@ struct addrdec_t {
    unsigned row;
    unsigned col;
    unsigned burst;
+
+   unsigned sub_partition; 
 };
 
 class linear_to_raw_address_translation {
 public:
    linear_to_raw_address_translation();
    void addrdec_setoption(option_parser_t opp);
-   void init(unsigned int nchips); 
+   void init(unsigned int n_channel, unsigned int n_sub_partition_in_channel); 
 
    // accessors
    void addrdec_tlx(new_addr_type addr, addrdec_t *tlx) const; 
@@ -78,7 +80,8 @@ private:
    new_addr_type addrdec_mask[N_ADDRDEC];
    
    unsigned int gap;
-   int Nchips;
+   int m_n_channel;
+   int m_n_sub_partition_in_channel; 
 };
 
 #endif