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authorMahmoud <[email protected]>2019-10-16 15:35:04 -0400
committerMahmoud <[email protected]>2019-10-16 15:35:04 -0400
commit2f2ee7256ffd03e9bce838f74651254c1588cb39 (patch)
treed713d6d2ae8f8d94135fe48f944272e338e85854 /src/gpgpu-sim/dram.cc
parentbce4e08d51e3f5817f174f639c56f34104b6efe1 (diff)
fixing the IPOLY L2 and Dram indexing
Diffstat (limited to 'src/gpgpu-sim/dram.cc')
-rw-r--r--src/gpgpu-sim/dram.cc25
1 files changed, 24 insertions, 1 deletions
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index 9c33822..a056371 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -210,10 +210,33 @@ dram_req_t::dram_req_t( class mem_fetch *mf, unsigned banks, unsigned dram_bnk_i
case BITWISE_XORING_BK_INDEX:
{
//xoring bank bits with lower bits of the page
- int lbank = log2(banks);
+ int lbank = LOGB2(banks);
bk = tlx.bk ^ (tlx.row & ((1<<lbank)-1));
break;
}
+ case IPOLY_BK_INDEX:
+ {
+ /*IPOLY for bank indexing function from "Pseudo-randomly interleaved memory."
+ * Rau, B. R et al.
+ * ISCA 1991
+ * http://citeseerx.ist.psu.edu/viewdoc/download;jsessionid=348DEA37A3E440473B3C075EAABC63B6?doi=10.1.1.12.7149&rep=rep1&type=pdf
+ */
+ if (banks == 16) {
+ std::bitset<64> a(tlx.row);
+ std::bitset<4> b(tlx.bk);
+ b[0] = a[11]^a[10]^a[9]^a[8]^a[6]^a[4]^a[3]^a[0]^b[0];
+ b[1] = a[12]^a[8]^a[7]^a[6]^a[5]^a[3]^a[1]^a[0]^b[1];
+ b[2] = a[9]^a[8]^a[7]^a[6]^a[4]^a[2]^a[1]^b[2];
+ b[3] = a[10]^a[9]^a[8]^a[7]^a[5]^a[3]^a[2]^b[3];
+ bk = b.to_ulong();
+ assert(bk < banks);
+ }
+ else{ /* Else incorrect number of channels for the hashing function */
+ assert("\nGPGPU-Sim memory_banking indexing error: The number of banks should be "
+ "16 for the hashing IPOLY index function.\n" && 0);
+ }
+ break;
+ }
case CUSTOM_BK_INDEX:
/* No custom set function implemented */
//Do you custom index here