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authorTayler Hetherington <[email protected]>2012-11-30 21:29:42 -0800
committerAndrew Boktor <[email protected]>2014-08-14 13:49:22 -0700
commit36ce0f2243fd0723a746b3c2f5f0651577312400 (patch)
treee79475e75f800ad34b4851ea710c4ee409f5bd72 /src/gpgpu-sim/dram.cc
parent08ec3343d0bca75e63e130266f75f8242f22050b (diff)
Merging Power model into Fermi
//depot/gpgpu_sim_research/fermi_power/distribution/... to //depot/gpgpu_sim_research/fermi/distribution/... [git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14723]
Diffstat (limited to 'src/gpgpu-sim/dram.cc')
-rw-r--r--src/gpgpu-sim/dram.cc32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index a173a52..3594198 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -419,6 +419,17 @@ void dram_t::cycle()
#endif
}
+void dram_t::get_access_stats(unsigned &total_access, unsigned &total_reads, unsigned &total_writes,unsigned &total_l2_read_access,unsigned &total_l2_read_miss,unsigned &total_l2_write_access,unsigned &total_l2_write_miss ){
+ total_access += m_stats->total_n_access;
+ total_reads += m_stats->total_n_reads;
+ total_writes += m_stats->total_n_writes;
+ total_l2_read_access += m_stats->L2_read_access;
+ total_l2_read_miss += m_stats->L2_read_miss;
+ total_l2_write_access += m_stats->L2_write_access;
+ total_l2_write_miss += m_stats->L2_write_miss;
+
+}
+
//if mrq is being serviced by dram, gets popped after CL latency fulfilled
class mem_fetch* dram_t::pop()
{
@@ -525,3 +536,24 @@ void dram_t::visualizer_print( gzFile visualizer_file )
m_stats->mem_access_type_stats[TEXTURE_ACC_R][id][j]);
}
}
+
+
+void dram_t::set_dram_power_stats( unsigned &cmd,
+ unsigned &activity,
+ unsigned &nop,
+ unsigned &act,
+ unsigned &pre,
+ unsigned &rd,
+ unsigned &wr,
+ unsigned &req) const{
+
+ // Point power performance counters to low-level DRAM counters
+ cmd = n_cmd;
+ activity = n_activity;
+ nop = n_nop;
+ act = n_act;
+ pre = n_pre;
+ rd = n_rd;
+ wr = n_wr;
+ req = n_req;
+}