Redesigned the memory partition unit to support multiple L2 cache banks per partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]

1 files changed, 6 insertions, 1 deletions

diff --git a/src/gpgpu-sim/dram.cc b/src/gpgpu-sim/dram.cc
index f28db2f..92c9727 100644
--- a/src/gpgpu-sim/dram.cc
+++ b/src/gpgpu-sim/dram.cc
@@ -421,11 +421,16 @@ void dram_t::cycle()
 }
 
 //if mrq is being serviced by dram, gets popped after CL latency fulfilled
-class mem_fetch* dram_t::pop() 
+class mem_fetch* dram_t::return_queue_pop() 
 {
     return returnq->pop();
 }
 
+class mem_fetch* dram_t::return_queue_top() 
+{
+    return returnq->top();
+}
+
 void dram_t::print( FILE* simFile) const
 {
    unsigned i;