Redesigned the memory partition unit to support multiple L2 cache banks per partition. Each L2 cache banks has its own connection to the interconnection network to allow L2 bandwidth to scale without increase the number of memory parttiion units.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 16613]

1 files changed, 2 insertions, 1 deletions

diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index 8c0a2b8..a8bff14 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -104,7 +104,8 @@ public:
    unsigned int queue_limit() const;
    void visualizer_print( gzFile visualizer_file );
 
-   class mem_fetch* pop();
+   class mem_fetch* return_queue_pop();
+   class mem_fetch* return_queue_top();
    void push( class mem_fetch *data );
    void cycle();
    void dram_log (int task);