Adding HBM model

1 files changed, 54 insertions, 5 deletions

diff --git a/src/gpgpu-sim/dram.h b/src/gpgpu-sim/dram.h
index a8bff14..0ec5166 100644
--- a/src/gpgpu-sim/dram.h
+++ b/src/gpgpu-sim/dram.h
@@ -31,9 +31,15 @@
 
 #include "delayqueue.h"
 #include <set>
+#include <vector>
+#include <bitset>
+#include <sstream>
+#include <string>
+#include <fstream>
 #include <zlib.h>
 #include <stdio.h>
 #include <stdlib.h>
+#include<iomanip>
 
 #define READ 'R'  //define read and write states
 #define WRITE 'W'
@@ -42,7 +48,7 @@
 
 class dram_req_t {
 public:
-   dram_req_t( class mem_fetch *data );
+   dram_req_t( class mem_fetch *data , unsigned banks, unsigned dram_bnk_indexing_policy);
 
    unsigned int row;
    unsigned int col;
@@ -106,6 +112,7 @@ public:
 
    class mem_fetch* return_queue_pop();
    class mem_fetch* return_queue_top();
+
    void push( class mem_fetch *data );
    void cycle();
    void dram_log (int task);
@@ -123,17 +130,24 @@ public:
 								unsigned &wr,
 								unsigned &req) const;
 
-private:
-   void scheduler_fifo();
-   void scheduler_frfcfs();
+
 
    const struct memory_config *m_config;
 
+private:
    bankgrp_t **bkgrp;
 
    bank_t **bk;
    unsigned int prio;
 
+   unsigned get_bankgrp_number(unsigned i);
+
+   void scheduler_fifo();
+   void scheduler_frfcfs();
+
+   bool issue_col_command(int j);
+   bool issue_row_command(int j);
+
    unsigned int RRDc;
    unsigned int CCDc;
    unsigned int RTWc;   //read to write penalty applies across banks
@@ -146,7 +160,7 @@ private:
    fifo_pipeline<dram_req_t> *rwq;
    fifo_pipeline<dram_req_t> *mrqq;
    //buffer to hold packets when DRAM processing is over
-   //should be filled with dram clock and popped with l2or icnt clock 
+   //should be filled with dram clock and popped with l2or icnt clock
    fifo_pipeline<mem_fetch> *returnq;
 
    unsigned int dram_util_bins[10];
@@ -158,11 +172,46 @@ private:
    unsigned int n_nop;
    unsigned int n_act;
    unsigned int n_pre;
+   unsigned int n_ref;
    unsigned int n_rd;
+   unsigned int n_rd_L2_A;
    unsigned int n_wr;
+   unsigned int n_wr_WB;
    unsigned int n_req;
    unsigned int max_mrqs_temp;
 
+   unsigned wasted_bw_row;
+   unsigned wasted_bw_col;
+   unsigned util_bw;
+   unsigned idle_bw;
+   unsigned RCDc_limit;
+   unsigned CCDLc_limit;
+   unsigned CCDLc_limit_alone;
+   unsigned CCDc_limit;
+   unsigned WTRc_limit;
+   unsigned WTRc_limit_alone;
+   unsigned RCDWRc_limit;
+   unsigned RTWc_limit;
+   unsigned RTWc_limit_alone;
+   unsigned rwq_limit;
+
+   //row locality, BLP and other statistics
+   unsigned long  access_num;
+   unsigned long long hits_num;
+   unsigned long long banks_1time;
+   unsigned long long banks_acess_total;
+   unsigned long long banks_acess_total_after;
+   unsigned long long banks_time_rw;
+   unsigned long long banks_access_rw_total;
+   unsigned long long banks_time_ready;
+   unsigned long long banks_access_ready_total;
+   unsigned long long issued_two;
+   unsigned long long issued_total;
+   unsigned long long issued_total_row;
+   unsigned long long issued_total_col;
+   double write_to_read_ratio_blp_rw_average;
+   unsigned long long bkgrp_parallsim_rw;
+
    unsigned int bwutil;
    unsigned int max_mrqs;
    unsigned int ave_mrqs;