Merge pull request #6 from abdallm/dev-purdue-integration

HBM model + all Mahmoud's changes to the sim

1 files changed, 96 insertions, 23 deletions

diff --git a/src/gpgpu-sim/dram_sched.cc b/src/gpgpu-sim/dram_sched.cc
index 8303e86..f754d36 100644
--- a/src/gpgpu-sim/dram_sched.cc
+++ b/src/gpgpu-sim/dram_sched.cc
@@ -36,6 +36,7 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem
    m_config = config;
    m_stats = stats;
    m_num_pending = 0;
+   m_num_write_pending = 0;
    m_dram = dm;
    m_queue = new std::list<dram_req_t*>[m_config->nbk];
    m_bins = new std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >[ m_config->nbk ];
@@ -49,15 +50,36 @@ frfcfs_scheduler::frfcfs_scheduler( const memory_config *config, dram_t *dm, mem
       curr_row_service_time[i] = 0;
       row_service_timestamp[i] = 0;
    }
+   if(m_config->seperate_write_queue_enabled) {
+	   m_write_queue = new std::list<dram_req_t*>[m_config->nbk];
+	   m_write_bins = new std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >[ m_config->nbk ];
+	   m_last_write_row = new std::list<std::list<dram_req_t*>::iterator>*[ m_config->nbk ];
+
+	   for ( unsigned i=0; i < m_config->nbk; i++ ) {
+	         m_write_queue[i].clear();
+	         m_write_bins[i].clear();
+	         m_last_write_row[i] = NULL;
+	      }
+   }
+   m_mode = READ_MODE;
 
 }
 
 void frfcfs_scheduler::add_req( dram_req_t *req )
 {
-   m_num_pending++;
-   m_queue[req->bk].push_front(req);
-   std::list<dram_req_t*>::iterator ptr = m_queue[req->bk].begin();
-   m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front
+  if(m_config->seperate_write_queue_enabled && req->data->is_write()) {
+	  assert(m_num_write_pending < m_config->gpgpu_frfcfs_dram_write_queue_size);
+	  m_num_write_pending++;
+	  m_write_queue[req->bk].push_front(req);
+	  std::list<dram_req_t*>::iterator ptr = m_write_queue[req->bk].begin();
+	  m_write_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front
+  } else {
+	   assert(m_num_pending < m_config->gpgpu_frfcfs_dram_sched_queue_size);
+	   m_num_pending++;
+	   m_queue[req->bk].push_front(req);
+	   std::list<dram_req_t*>::iterator ptr = m_queue[req->bk].begin();
+	   m_bins[req->bk][req->row].push_front( ptr ); //newest reqs to the front
+  }
 }
 
 void frfcfs_scheduler::data_collection(unsigned int bank)
@@ -78,41 +100,90 @@ void frfcfs_scheduler::data_collection(unsigned int bank)
 
 dram_req_t *frfcfs_scheduler::schedule( unsigned bank, unsigned curr_row )
 {
-   if ( m_last_row[bank] == NULL ) {
-      if ( m_queue[bank].empty() )
+   //row
+   bool rowhit = true;
+   std::list<dram_req_t*> *m_current_queue = m_queue;
+   std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> > *m_current_bins = m_bins ;
+   std::list<std::list<dram_req_t*>::iterator> **m_current_last_row = m_last_row;
+
+   if(m_config->seperate_write_queue_enabled) {
+	   if(m_mode == READ_MODE &&
+			  ((m_num_write_pending >= m_config->write_high_watermark )
+			   || (m_queue[bank].empty() && !m_write_queue[bank].empty()))) {
+		   m_mode = WRITE_MODE;
+	   }
+	   else if(m_mode == WRITE_MODE &&
+				  (( m_num_write_pending < m_config->write_low_watermark )
+				   || (!m_queue[bank].empty() && m_write_queue[bank].empty()))){
+		   m_mode = READ_MODE;
+	   }
+   }
+
+   if(m_mode == WRITE_MODE) {
+	   m_current_queue = m_write_queue;
+	   m_current_bins = m_write_bins ;
+	   m_current_last_row = m_last_write_row;
+   }
+
+   if ( m_current_last_row[bank] == NULL ) {
+      if ( m_current_queue[bank].empty() )
          return NULL;
 
-      std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >::iterator bin_ptr = m_bins[bank].find( curr_row );
-      if ( bin_ptr == m_bins[bank].end()) {
-         dram_req_t *req = m_queue[bank].back();
-         bin_ptr = m_bins[bank].find( req->row );
-         assert( bin_ptr != m_bins[bank].end() ); // where did the request go???
-         m_last_row[bank] = &(bin_ptr->second);
+      std::map<unsigned,std::list<std::list<dram_req_t*>::iterator> >::iterator bin_ptr = m_current_bins[bank].find( curr_row );
+      if ( bin_ptr == m_current_bins[bank].end()) {
+         dram_req_t *req = m_current_queue[bank].back();
+         bin_ptr = m_current_bins[bank].find( req->row );
+         assert( bin_ptr != m_current_bins[bank].end() ); // where did the request go???
+         m_current_last_row[bank] = &(bin_ptr->second);
          data_collection(bank);
+         rowhit = false;
       } else {
-         m_last_row[bank] = &(bin_ptr->second);
-
+    	  m_current_last_row[bank] = &(bin_ptr->second);
+         rowhit = true;
       }
    }
-   std::list<dram_req_t*>::iterator next = m_last_row[bank]->back();
+   std::list<dram_req_t*>::iterator next = m_current_last_row[bank]->back();
    dram_req_t *req = (*next);
 
+   //rowblp stats
+    m_dram->access_num++;
+    bool is_write = req->data->is_write();
+    if(is_write)
+  	  m_dram->write_num++;
+    else
+  	  m_dram->read_num++;
+
+    if(rowhit) {
+     m_dram->hits_num++;
+     if(is_write)
+    	  m_dram->hits_write_num++;
+      else
+    	  m_dram->hits_read_num++;
+    }
+
    m_stats->concurrent_row_access[m_dram->id][bank]++;
    m_stats->row_access[m_dram->id][bank]++;
-   m_last_row[bank]->pop_back();
+   m_current_last_row[bank]->pop_back();
 
-   m_queue[bank].erase(next);
-   if ( m_last_row[bank]->empty() ) {
-      m_bins[bank].erase( req->row );
-      m_last_row[bank] = NULL;
+   m_current_queue[bank].erase(next);
+   if ( m_current_last_row[bank]->empty() ) {
+	   m_current_bins[bank].erase( req->row );
+	   m_current_last_row[bank] = NULL;
    }
 #ifdef DEBUG_FAST_IDEAL_SCHED
    if ( req )
       printf("%08u : DRAM(%u) scheduling memory request to bank=%u, row=%u\n", 
              (unsigned)gpu_sim_cycle, m_dram->id, req->bk, req->row );
 #endif
-   assert( req != NULL && m_num_pending != 0 ); 
-   m_num_pending--;
+
+   if(m_config->seperate_write_queue_enabled && req->data->is_write()) {
+	   assert( req != NULL && m_num_write_pending != 0 );
+	   m_num_write_pending--;
+   }
+   else {
+	   assert( req != NULL && m_num_pending != 0 );
+	   m_num_pending--;
+   }
 
    return req;
 }
@@ -129,7 +200,7 @@ void dram_t::scheduler_frfcfs()
 {
    unsigned mrq_latency;
    frfcfs_scheduler *sched = m_frfcfs_scheduler;
-   while ( !mrqq->empty() && (!m_config->gpgpu_frfcfs_dram_sched_queue_size || sched->num_pending() < m_config->gpgpu_frfcfs_dram_sched_queue_size)) {
+   while ( !mrqq->empty() ) {
       dram_req_t *req = mrqq->pop();
 
       // Power stats
@@ -160,6 +231,8 @@ void dram_t::scheduler_frfcfs()
             bk[b]->mrq = req;
             if (m_config->gpgpu_memlatency_stat) {
                mrq_latency = gpu_sim_cycle + gpu_tot_sim_cycle - bk[b]->mrq->timestamp;
+               m_stats->tot_mrq_latency += mrq_latency;
+               m_stats->tot_mrq_num++;
                bk[b]->mrq->timestamp = gpu_tot_sim_cycle + gpu_sim_cycle;
                m_stats->mrq_lat_table[LOGB2(mrq_latency)]++;
                if (mrq_latency > m_stats->max_mrq_latency) {