Modified the cache hierarchy, reorganized code to eliminate code replication, implemented write allocate / write back policies in L2 cache, added configurable parameters in gpgpusim.config ("W" = Write Allocate, "N" = No write allocate -> "P" = Private, "S" = shared), modified the cache configuration lines to always be separated by ":" instead of ":" and ",", and modified L1 and L2 data cache to be "Write Back" caches instead of "Read Only".

Still need to implement Ahmed's sectored cache implementation.

[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14081]

1 files changed, 2 insertions, 2 deletions

diff --git a/src/gpgpu-sim/gpu-cache.cc b/src/gpgpu-sim/gpu-cache.cc
index 043c583..ace2686 100644
--- a/src/gpgpu-sim/gpu-cache.cc
+++ b/src/gpgpu-sim/gpu-cache.cc
@@ -37,7 +37,7 @@ tag_array::~tag_array()
 tag_array::tag_array( const cache_config &config, int core_id, int type_id ) 
 : m_config(config), m_access(0), m_miss(0), m_pending_hit(0)
 {
-    assert( m_config.m_write_policy == READ_ONLY );
+    //assert( m_config.m_write_policy == READ_ONLY ); Old assert
     m_lines = new cache_block_t[ config.get_num_lines()];
 
     // initialize snapshot counters for visualizer
@@ -49,7 +49,7 @@ tag_array::tag_array( const cache_config &config, int core_id, int type_id )
 }
 
 enum cache_request_status tag_array::probe( new_addr_type addr, unsigned &idx ) const {
-    assert( m_config.m_write_policy == READ_ONLY );
+    //assert( m_config.m_write_policy == READ_ONLY );
     unsigned set_index = m_config.set_index(addr);
     new_addr_type tag = m_config.tag(addr);