diff options
| author | Tayler Hetherington <[email protected]> | 2012-09-28 10:37:26 -0800 |
|---|---|---|
| committer | Andrew Boktor <[email protected]> | 2014-08-14 13:49:21 -0700 |
| commit | 495cfab5e38d80c8daddf170dce84f3e2d08f537 (patch) | |
| tree | 7bf683cc9bf24130bd5b61062ce26e4469f16566 /src/gpgpu-sim/gpu-cache.h | |
| parent | 3bcf37cfe0514e4ee13fcab94778440b17124b28 (diff) | |
gpu-cache revision #3. Now adding in function pointers for l1/l2 cache access functions. Removes the multiple long flaky branches in the access functions (caused by multiple config options) and replaces them with a single function that is set in the constructor to reflect the current configuration.
[git-p4: depot-paths = "//depot/gpgpu_sim_research/fermi/distribution/": change = 14198]
Diffstat (limited to 'src/gpgpu-sim/gpu-cache.h')
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.h | 58 |
1 files changed, 53 insertions, 5 deletions
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index 431760a..86183d3 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -98,7 +98,8 @@ enum write_policy_t { READ_ONLY, WRITE_BACK, WRITE_THROUGH, - WRITE_EVICT + WRITE_EVICT, + LOCAL_WB_GLOBAL_WT }; enum allocation_policy_t { @@ -152,6 +153,7 @@ public: case 'B': m_write_policy = WRITE_BACK; break; case 'T': m_write_policy = WRITE_THROUGH; break; case 'E': m_write_policy = WRITE_EVICT; break; + case 'L': m_write_policy = LOCAL_WB_GLOBAL_WT; break; default: exit_parse_error(); } switch (ap) { @@ -441,6 +443,29 @@ public: : baseline_cache(name,config,core_id,type_id,memport,status) { m_memfetch_creator=mfcreator; + + // Set read hit function + m_rd_hit = &data_cache::rd_hit_base; + + // Set read miss function + m_rd_miss = &data_cache::rd_miss_base; + + // Set write hit function + switch(m_config.m_write_policy){ + case READ_ONLY: assert(0 && "Error: Writable Data_cache set as READ_ONLY\n"); break; // READ_ONLY is now a separate cache class, config is deprecated + case WRITE_BACK: m_wr_hit = &data_cache::wr_hit_wb; break; + case WRITE_THROUGH: m_wr_hit = &data_cache::wr_hit_wt; break; + case WRITE_EVICT: m_wr_hit = &data_cache::wr_hit_we; break; + case LOCAL_WB_GLOBAL_WT: m_wr_hit = &data_cache::wr_hit_global_we_local_wb; break; + default: assert(0 && "Error: Must set valid cache write policy\n"); break; // Need to set a write hit function + } + + // Set write miss function + switch(m_config.m_write_alloc_policy){ + case WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_wa; break; + case NO_WRITE_ALLOCATE: m_wr_miss = &data_cache::wr_miss_no_wa; break; + default: assert(0 && "Error: Must set valid cache write miss policy\n"); break; // Need to set a write miss function + } } protected: @@ -449,12 +474,34 @@ protected: // Functions for data cache access /// Sends write request to lower level memory (write or writeback) void send_write_request(mem_fetch *mf, cache_event request, unsigned time, std::list<cache_event> &events); - /// Sends read request, and possible write-back request, to lower level memory for a write miss with write-allocate - bool send_write_allocate(mem_fetch *mf, new_addr_type addr, new_addr_type block_addr, unsigned cache_index, unsigned time, std::list<cache_event> &events); + + + // Member Function pointers - Set by configuration options to the functions below each grouping + /******* Write-hit configs *******/ + enum cache_request_status (data_cache::*m_wr_hit)(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); /// Marks block as MODIFIED and updates block LRU - void write_back_hit(new_addr_type block_addr, unsigned time, unsigned cache_index); + enum cache_request_status wr_hit_wb(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); // write-back + enum cache_request_status wr_hit_wt(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); // write-through /// Marks block as INVALID and sends write request to lower level memory - bool do_write_evict(mem_fetch *mf, unsigned time, unsigned cache_index, std::list<cache_event> &events); + enum cache_request_status wr_hit_we(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); // write-evict + enum cache_request_status wr_hit_global_we_local_wb(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); // global write-evict, local write-back + + + /******* Write-miss configs *******/ + enum cache_request_status (data_cache::*m_wr_miss)(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); + /// Sends read request, and possible write-back request, to lower level memory for a write miss with write-allocate + enum cache_request_status wr_miss_wa(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); // write-allocate + enum cache_request_status wr_miss_no_wa(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); // no write-allocate + + // Currently no separate functions for reads + /******* Read-hit configs *******/ + enum cache_request_status (data_cache::*m_rd_hit)(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); + enum cache_request_status rd_hit_base(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); + + /******* Read-miss configs *******/ + enum cache_request_status (data_cache::*m_rd_miss)(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); + enum cache_request_status rd_miss_base(new_addr_type addr, unsigned cache_index, mem_fetch *mf, unsigned time, std::list<cache_event> &events); + }; /// This is meant to model the first level data cache in Fermi. @@ -468,6 +515,7 @@ public: : data_cache(name,config,core_id,type_id,memport,mfcreator,status){} virtual enum cache_request_status access( new_addr_type addr, mem_fetch *mf, unsigned time, std::list<cache_event> &events ); + }; /// Models second level shared cache with global write-back and write-allocate policies |
