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| author | Tim Rogers <[email protected]> | 2019-08-26 14:57:01 -0400 |
|---|---|---|
| committer | GitHub <[email protected]> | 2019-08-26 14:57:01 -0400 |
| commit | 6be23a1b36a3311c7dafc45a5e692e38cb351337 (patch) | |
| tree | 65583782519448ef56e6b60e8067d94526f2b149 /src/gpgpu-sim/gpu-cache.h | |
| parent | fd91575e7dcc40653ea0279ef33d845d1d473ffa (diff) | |
| parent | a168a2c7224ea59c9ea7523be1f46893531bdc63 (diff) | |
Merge pull request #27 from mkhairy/dev
Merging a few latency fixes in the memory system
Diffstat (limited to 'src/gpgpu-sim/gpu-cache.h')
| -rw-r--r-- | src/gpgpu-sim/gpu-cache.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-cache.h b/src/gpgpu-sim/gpu-cache.h index be33d96..6f39221 100644 --- a/src/gpgpu-sim/gpu-cache.h +++ b/src/gpgpu-sim/gpu-cache.h @@ -584,6 +584,7 @@ public: m_nset_log2 = LOGB2(m_nset); m_valid = true; m_atom_sz = (m_cache_type == SECTOR)? SECTOR_SIZE : m_line_sz; + m_sector_sz_log2 = LOGB2(SECTOR_SIZE); original_m_assoc = m_assoc; //For more details about difference between FETCH_ON_WRITE and WRITE VALIDAE policies @@ -734,6 +735,7 @@ protected: unsigned m_nset_log2; unsigned m_assoc; unsigned m_atom_sz; + unsigned m_sector_sz_log2; unsigned original_m_assoc; bool m_is_streaming; @@ -775,7 +777,9 @@ class l1d_cache_config : public cache_config{ public: l1d_cache_config() : cache_config(){} virtual unsigned set_index(new_addr_type addr) const; + unsigned set_bank(new_addr_type addr) const; unsigned l1_latency; + unsigned l1_banks; }; class l2_cache_config : public cache_config { |