diff options
| author | Suchita Pati <[email protected]> | 2018-05-21 00:26:04 +0000 |
|---|---|---|
| committer | tgrogers-purdue <[email protected]> | 2018-05-21 00:26:04 +0000 |
| commit | 1b6389ab70211b622f02b149bfb20ae68a2e2552 (patch) | |
| tree | 9e75d6d0474d1cfbf27501e2461022c593b6f740 /src/gpgpu-sim/gpu-sim.cc | |
| parent | 0f8c407eea99e1622486127912a83ef3e0dcf397 (diff) | |
| parent | f405cb9484a8b0f961bd7c143bebf1fcb17546da (diff) | |
Merged in suchitapati/gpgpusim-cudnn-05-01-18 (pull request #7)
Support for -gpgpu_registers_per_block and addition of -save_embedded_ptx 1 to config files for mnistCUDNN
Approved-by: tgrogers-purdue <[email protected]>
Diffstat (limited to 'src/gpgpu-sim/gpu-sim.cc')
| -rw-r--r-- | src/gpgpu-sim/gpu-sim.cc | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/gpgpu-sim/gpu-sim.cc b/src/gpgpu-sim/gpu-sim.cc index 892b245..d0b362f 100644 --- a/src/gpgpu-sim/gpu-sim.cc +++ b/src/gpgpu-sim/gpu-sim.cc @@ -256,6 +256,9 @@ void shader_core_config::reg_options(class OptionParser * opp) option_parser_register(opp, "-gpgpu_shader_registers", OPT_UINT32, &gpgpu_shader_registers, "Number of registers per shader core. Limits number of concurrent CTAs. (default 8192)", "8192"); + option_parser_register(opp, "-gpgpu_registers_per_block", OPT_UINT32, &gpgpu_registers_per_block, + "Maximum number of registers per CTA. (default 8192)", + "8192"); option_parser_register(opp, "-gpgpu_shader_cta", OPT_UINT32, &max_cta_per_core, "Maximum number of concurrent CTAs in shader (default 8)", "8"); @@ -683,6 +686,11 @@ int gpgpu_sim::num_registers_per_core() const return m_shader_config->gpgpu_shader_registers; } +int gpgpu_sim::num_registers_per_block() const +{ + return m_shader_config->gpgpu_registers_per_block; +} + int gpgpu_sim::wrp_size() const { return m_shader_config->warp_size; |